diff --git a/src/gateware/ebaz4205.py b/src/gateware/ebaz4205.py
index 744abf3..3359a10 100644
--- a/src/gateware/ebaz4205.py
+++ b/src/gateware/ebaz4205.py
@@ -87,16 +87,7 @@ class EBAZ4205(SoCCore):
         platform.add_extension(_ps)
         platform.add_extension(_ddr)
 
-        ## Uncomment if your EBAZ4205 doesn't have a PHY XTAL
-        ## Clock for PHY is tied to pin U18
-        # platform.add_extension(
-        #     [
-        #         ("phy_clk", 0, Pins("U18"), IOStandard("LVCMOS33")),
-        #     ]
-        # )
-
         gmii = platform.request("gmii")
-
         platform.add_period_constraint(gmii.rx_clk, 10)
         platform.add_period_constraint(gmii.tx_clk, 10)
         platform.add_platform_command(
@@ -135,11 +126,6 @@ class EBAZ4205(SoCCore):
             self.ps7.enet0.enet.gmii.rx_dv.eq(gmii.rx_dv),
         ]
 
-        ## Uncomment if your EBAZ4205 doesn't have a PHY XTAL
-        ## Left for the user to do, setup a 25 MHz clock for phy_clk.
-        # phy_clk = platform.request("phy_clk")
-        # ...
-
         # MDIO
         mdio = platform.request("mdio")
         self.comb += [