forked from M-Labs/artiq-zynq
Clean up warning take 2
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@ -454,7 +454,7 @@ fn set_fclk0_freq(clk: RtioClock, cfg: &Config) {
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.modify(|_, w| w.divisor0(divisor0).divisor1(divisor1));
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});
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} else {
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warn!("Could not set fclk0 for target frequency of '{:?}'", target_freq);
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warn!("Could not set fclk0 for target frequency: '{:?}'", target_freq);
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}
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}
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