zynq-rs/src
2019-05-23 15:36:34 +02:00
..
cortex_a9 PoC: boot, uart output in qemu 2019-05-05 14:56:23 +02:00
eth eth: add regs and init 2019-05-07 19:28:33 +02:00
uart uart: add more channel_sts flags, wait for tx_fifo_empty() before sending 2019-05-23 15:36:34 +02:00
main.rs use uart1 with more configuration 2019-05-21 01:30:54 +02:00
regs.rs slcr: with_slcr() for unlock/lock 2019-05-21 01:30:17 +02:00
slcr.rs uart: wait for reset 2019-05-21 02:53:59 +02:00