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zynq::ddr: don't overwrite slcr.ddr_pll_ctrl

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Astro 2019-10-27 22:54:34 +01:00
parent 637bb35f43
commit f199ac68b4
1 changed files with 0 additions and 4 deletions
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4
src/zynq/ddr/mod.rs
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@ -42,10 +42,6 @@ impl DdrRam {
let ddr2x_clk_divisor = 3 * ddr3x_clk_divisor / 2; let ddr2x_clk_divisor = 3 * ddr3x_clk_divisor / 2;
slcr::RegisterBlock::unlocked(|slcr| { slcr::RegisterBlock::unlocked(|slcr| {
slcr.ddr_pll_ctrl.write(
slcr::PllCtrl::zeroed()
);
slcr.ddr_clk_ctrl.write( slcr.ddr_clk_ctrl.write(
slcr::DdrClkCtrl::zeroed() slcr::DdrClkCtrl::zeroed()
.ddr_2xclkact(true) .ddr_2xclkact(true)