mwojcik/zynq-rs
1
0
Fork 0
forked from M-Labs/zynq-rs
Code Issues Pull Requests Projects Releases Wiki Activity

zynq::ddr: fix typo

Browse Source
This commit is contained in:
Astro 2019-10-28 23:58:25 +01:00
parent 7cdf6c0918
commit ceeaa6427e
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/zynq/ddr/mod.rs
View File

@ -36,7 +36,7 @@ impl DdrRam {
/// 10.6.1 DDR Clock Initialization
fn clock_setup() -> CpuClocks {
let clocks = CpuClocks::get();
CpuClocks::enable_ddr(clocks.cpu);
CpuClocks::enable_ddr(clocks.arm);
let clocks = CpuClocks::get();
let ddr3x_clk_divisor = ((clocks.ddr - 1) / DDR_FREQ + 1).min(255) as u8;