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zynq::ddr: fix typo

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Astro 2019-10-28 23:58:25 +01:00
parent 7cdf6c0918
commit ceeaa6427e
1 changed files with 1 additions and 1 deletions
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src/zynq/ddr/mod.rs
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@ -36,7 +36,7 @@ impl DdrRam {
/// 10.6.1 DDR Clock Initialization /// 10.6.1 DDR Clock Initialization
fn clock_setup() -> CpuClocks { fn clock_setup() -> CpuClocks {
let clocks = CpuClocks::get(); let clocks = CpuClocks::get();
CpuClocks::enable_ddr(clocks.cpu); CpuClocks::enable_ddr(clocks.arm);
let clocks = CpuClocks::get(); let clocks = CpuClocks::get();
let ddr3x_clk_divisor = ((clocks.ddr - 1) / DDR_FREQ + 1).min(255) as u8; let ddr3x_clk_divisor = ((clocks.ddr - 1) / DDR_FREQ + 1).min(255) as u8;