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eth: fix initialization

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This commit is contained in:
Astro 2019-06-04 23:48:09 +02:00
parent 6d15b82a3e
commit b9ca9324f0
2 changed files with 10 additions and 10 deletions
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15
src/eth/mod.rs
View File

@ -126,11 +126,13 @@ impl Eth {
slcr::RclkCtrl::zeroed()
.clkact(true)
);
// 0x0050_0801: 8, 5: 100 Mb/s
slcr.gem0_clk_ctrl.write(
slcr::ClkCtrl::zeroed()
.clkact(true)
.srcsel(slcr::PllSource::IoPll)
.divisor(10)
.divisor(8)
.divisor1(5)
);
});
@ -143,7 +145,7 @@ impl Eth {
Eth { regs }.init()
}
fn init(self) -> Self {
fn init(mut self) -> Self {
// Clear the Network Control register.
self.regs.net_ctrl.write(regs::NetCtrl::zeroed());
self.regs.net_ctrl.write(regs::NetCtrl::zeroed().clear_stat_regs(true));
@ -206,6 +208,7 @@ impl Eth {
regs::TxQbar::zeroed()
);
self.configure();
self
}
@ -233,13 +236,7 @@ impl Eth {
}
fn wait_phy_idle(&self) {
let mut timeout = 5_000_000;
while !self.regs.net_status.read().phy_mgmt_idle() {
timeout -= 1;
if timeout == 0 {
break
}
}
while !self.regs.net_status.read().phy_mgmt_idle() {}
}
}

5
src/slcr.rs
View File

@ -262,7 +262,10 @@ register_bit!(rclk_ctrl,
register!(clk_ctrl, ClkCtrl, RW, u32);
register_bits!(clk_ctrl,
/// Divisor for source clock
/// 2nd divisor for source clock
divisor1, u8, 20, 25);
register_bits!(clk_ctrl,
/// 1st divisor for source clock
divisor, u8, 8, 13);
register_bits_typed!(clk_ctrl,
/// Source to generate the ref clock