forked from M-Labs/zynq-rs
cortex_a9::mmu: make OCM region cachable
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@ -124,7 +124,7 @@ impl L1Table {
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tex: 0b101,
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tex: 0b101,
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domain: 0b1111,
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domain: 0b1111,
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exec: true,
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exec: true,
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cacheable: false,
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cacheable: true,
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bufferable: true,
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bufferable: true,
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});
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});
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/* (DDR cacheable) */
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/* (DDR cacheable) */
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