2019-06-22 07:34:47 +08:00
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use core::ops::{Deref, DerefMut};
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2020-06-11 05:20:43 +08:00
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use alloc::{vec, vec::Vec};
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2020-06-18 07:25:43 +08:00
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use libcortex_a9::{cache::dcc_slice, UncachedSlice};
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2019-12-18 06:35:58 +08:00
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use libregister::*;
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2020-03-29 06:30:39 +08:00
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use super::{Buffer, regs};
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2019-06-09 07:02:10 +08:00
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/// Descriptor entry
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2019-09-29 07:39:12 +08:00
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#[repr(C, align(0x08))]
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2019-06-22 07:34:47 +08:00
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pub struct DescEntry {
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2019-06-09 07:02:10 +08:00
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word0: DescWord0,
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word1: DescWord1,
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}
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2019-10-31 10:15:13 +08:00
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register!(desc_word0, DescWord0, VolatileCell, u32);
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2019-06-09 07:02:10 +08:00
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register_bits!(desc_word0, address, u32, 0, 31);
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2019-10-31 10:15:13 +08:00
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register!(desc_word1, DescWord1, VolatileCell, u32);
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2019-06-09 07:02:10 +08:00
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register_bits!(desc_word1, length, u16, 0, 13);
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register_bit!(desc_word1, last_buffer, 15);
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register_bit!(desc_word1, no_crc_append, 16);
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register_bits!(desc_word1, csum_offload_errors, u8, 20, 22);
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register_bit!(desc_word1, late_collision_tx_error, 26);
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register_bit!(desc_word1, ahb_frame_corruption, 27);
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register_bit!(desc_word1, retry_limit_exceeded, 29);
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2019-08-11 06:55:27 +08:00
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register_bit!(desc_word1,
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/// marks last descriptor in list
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wrap, 30);
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register_bit!(desc_word1,
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/// true if owned by software, false if owned by hardware
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used, 31);
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2019-06-10 02:28:33 +08:00
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2019-10-31 10:15:13 +08:00
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impl DescEntry {
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pub fn zeroed() -> Self {
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DescEntry {
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word0: DescWord0 { inner: VolatileCell::new(0) },
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word1: DescWord1 { inner: VolatileCell::new(0) },
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}
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}
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}
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2019-06-10 02:28:33 +08:00
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/// Number of descriptors
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pub const DESCS: usize = 8;
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#[repr(C)]
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2020-06-11 05:20:43 +08:00
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pub struct DescList {
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2020-06-18 07:25:43 +08:00
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list: UncachedSlice<DescEntry>,
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2020-06-11 05:20:43 +08:00
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buffers: Vec<Buffer>,
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2019-06-22 07:34:47 +08:00
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next: usize,
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2019-06-10 02:28:33 +08:00
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}
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2020-06-11 05:20:43 +08:00
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impl DescList {
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pub fn new(size: usize) -> Self {
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2020-06-18 07:25:43 +08:00
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let mut list = UncachedSlice::new(size, || DescEntry::zeroed())
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.unwrap();
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2020-06-11 05:20:43 +08:00
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let mut buffers = vec![Buffer::new(); size];
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2019-06-22 07:34:47 +08:00
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let last = list.len().min(buffers.len()) - 1;
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2019-10-18 06:03:17 +08:00
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// Sending seems to not work properly with only one packet
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// buffer (two duplicates get send with every packet), so
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// check that at least 2 are allocated, i.e. that the index of
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// the last one is at least one.
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assert!(last > 0);
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2019-06-22 07:34:47 +08:00
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for (i, (entry, buffer)) in list.iter_mut().zip(buffers.iter_mut()).enumerate() {
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let is_last = i == last;
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2020-03-29 06:30:39 +08:00
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let buffer_addr = &mut buffer.0[0] as *mut _ as u32;
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2019-06-22 07:34:47 +08:00
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assert!(buffer_addr & 0b11 == 0);
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entry.word0.write(
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2019-06-10 02:28:33 +08:00
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DescWord0::zeroed()
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.address(buffer_addr)
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);
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2019-06-22 07:34:47 +08:00
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entry.word1.write(
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2019-06-10 02:28:33 +08:00
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DescWord1::zeroed()
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.used(true)
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2019-06-22 07:34:47 +08:00
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.wrap(is_last)
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2019-06-24 08:15:11 +08:00
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// every frame contains 1 packet
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.last_buffer(true)
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);
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2019-06-10 02:28:33 +08:00
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}
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2019-06-22 07:34:47 +08:00
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DescList {
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2020-06-11 05:20:43 +08:00
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list,
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2019-06-22 07:34:47 +08:00
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buffers,
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next: 0,
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}
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}
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pub fn list_addr(&self) -> u32 {
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&self.list[0] as *const _ as u32
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}
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2019-07-05 06:44:53 +08:00
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pub fn send<'s: 'p, 'p>(&'s mut self, regs: &'s mut regs::RegisterBlock, length: usize) -> Option<PktRef<'p>> {
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2019-06-22 07:34:47 +08:00
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let list_len = self.list.len();
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let entry = &mut self.list[self.next];
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if entry.word1.read().used() {
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let buffer = &mut self.buffers[self.next][0..length];
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2019-11-04 09:31:40 +08:00
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entry.word1.write(DescWord1::zeroed()
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.length(length as u16)
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.last_buffer(true)
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.wrap(self.next >= list_len - 1)
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.used(true)
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);
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2019-06-22 07:34:47 +08:00
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self.next += 1;
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if self.next >= list_len {
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self.next = 0;
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}
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Some(PktRef { entry, buffer, regs })
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} else {
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// Still in use by HW (sending too fast, ring exceeded)
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None
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}
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}
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}
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/// Releases a buffer back to the HW upon Drop, and start the TX
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/// engine
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pub struct PktRef<'a> {
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entry: &'a mut DescEntry,
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buffer: &'a mut [u8],
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regs: &'a mut regs::RegisterBlock,
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}
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impl<'a> Drop for PktRef<'a> {
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fn drop(&mut self) {
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2020-06-19 00:07:50 +08:00
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// Write back all dirty cachelines of this buffer
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2020-06-18 07:25:43 +08:00
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dcc_slice(self.buffer);
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2020-06-19 00:07:50 +08:00
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2019-06-22 07:34:47 +08:00
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self.entry.word1.modify(|_, w| w.used(false));
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2019-06-25 07:32:43 +08:00
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if ! self.regs.tx_status.read().tx_go() {
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2020-06-19 00:07:50 +08:00
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// Start TX if not already running
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self.regs.net_ctrl.modify(|_, w| w.start_tx(true));
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2019-06-25 07:32:43 +08:00
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}
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2019-06-22 07:34:47 +08:00
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}
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}
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impl<'a> Deref for PktRef<'a> {
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type Target = [u8];
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fn deref(&self) -> &Self::Target {
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self.buffer
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}
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}
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impl<'a> DerefMut for PktRef<'a> {
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fn deref_mut(&mut self) -> &mut <Self as Deref>::Target {
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self.buffer
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2019-06-10 02:28:33 +08:00
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}
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}
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2019-07-03 05:29:16 +08:00
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/// TxToken for smoltcp support
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2020-06-11 05:20:43 +08:00
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pub struct Token<'a> {
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2019-07-03 05:29:16 +08:00
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pub regs: &'a mut regs::RegisterBlock,
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2020-06-11 05:20:43 +08:00
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pub desc_list: &'a mut DescList,
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2019-07-03 05:29:16 +08:00
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}
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2020-06-11 05:20:43 +08:00
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impl<'a> smoltcp::phy::TxToken for Token<'a> {
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2019-07-03 05:29:16 +08:00
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fn consume<R, F>(self, _timestamp: smoltcp::time::Instant, len: usize, f: F) -> smoltcp::Result<R>
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where F: FnOnce(&mut [u8]) -> smoltcp::Result<R>
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{
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match self.desc_list.send(self.regs, len) {
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None =>
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Err(smoltcp::Error::Exhausted),
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Some(mut pktref) => {
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let result = f(pktref.deref_mut());
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// TODO: on result.is_err() don;t send
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drop(pktref);
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result
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}
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}
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}
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}
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