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cfg_reg: reorganize bitmasks

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This commit is contained in:
occheung 2020-08-11 16:55:31 +08:00
parent 0df7ff71cf
commit e75c3d3342
1 changed files with 8 additions and 25 deletions
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33
src/config_register.rs
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@ -1,29 +1,6 @@
use embedded_hal::blocking::spi::Transfer;
use crate::Error;
/*
* Bit Masks for CFG_Write
*/
const RF_SW :u32 = 0x0000000F;
const LED :u32 = 0x000000F0;
const PROFILE :u32 = 0x00000700;
const IO_UPDATE :u32 = 0x00001000;
const MASK_NU :u32 = 0x0001E000;
const CLK_SEL0 :u32 = 0x00020000;
const SYNC_SEL :u32 = 0x00040000;
const RST :u32 = 0x00080000;
const IO_RST :u32 = 0x00100000;
const CLK_SEL1 :u32 = 0x00200000;
const DIV :u32 = 0x00C00000;
/*
* Bit Masks for CFG_Read
*/
const SMP_ERR :u32 = 0x000000F0;
const PLL_LOCK :u32 = 0x00000F00;
const IFC_MODE :u32 = 0x0000F000;
const PROTO_DEV :u32 = 0x007F0000;
/*
* Macro builder for bit masks
*/
@ -68,7 +45,8 @@ macro_rules! construct_bitmask {
}
construct_bitmask!(CFGMask;
RF_SW, 0, 4,
// Bitmasks for CFG write
RF_SW, 0, 4, // Reuse RF_SW for Status register
LED, 4, 4,
PROFILE, 8, 3,
IO_UPDATE, 12, 1,
@ -78,7 +56,12 @@ construct_bitmask!(CFGMask;
RST, 19, 1,
IO_RST, 20, 1,
CLK_SEL1, 21, 1,
DIV, 22, 2
DIV, 22, 2,
// BitMasks for CFG read
SMP_ERR, 4, 4,
PLL_LOCK, 8, 4,
IFC_MODE, 12, 4,
PROTO_KEY, 16, 7
);
pub struct ConfigRegister<SPI> {