forked from M-Labs/humpback-dds
cpld: auto invoke io update
This commit is contained in:
parent
9ec5698f63
commit
29abca72cd
70
src/lib.rs
70
src/lib.rs
@ -30,20 +30,22 @@ pub enum Error<E> {
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CSError,
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GetRefMutDataError,
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AttenuatorError,
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IOUpdateError,
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}
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/*
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* Basic structure for CPLD signal multiplexing
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*/
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#[derive(Debug)]
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pub struct CPLDData<SPI, CS0, CS1, CS2> {
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pub struct CPLDData<SPI, CS0, CS1, CS2, GPIO> {
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pub(crate) spi: SPI,
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pub(crate) chip_select: (CS0, CS1, CS2),
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pub(crate) io_update: GPIO,
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}
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#[derive(Debug)]
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pub struct CPLD<SPI, CS0, CS1, CS2> {
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pub(crate) data: cell::RefCell<CPLDData<SPI, CS0, CS1, CS2>>,
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pub struct CPLD<SPI, CS0, CS1, CS2, GPIO> {
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pub(crate) data: cell::RefCell<CPLDData<SPI, CS0, CS1, CS2, GPIO>>,
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}
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pub trait SelectChip {
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@ -51,12 +53,13 @@ pub trait SelectChip {
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fn select_chip(&mut self, chip: u8) -> Result<(), Self::Error>;
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}
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impl<SPI, CS0, CS1, CS2, E> SelectChip for CPLDData<SPI, CS0, CS1, CS2>
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impl<SPI, CS0, CS1, CS2, GPIO, E> SelectChip for CPLDData<SPI, CS0, CS1, CS2, GPIO>
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where
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SPI: Transfer<u8, Error = E>,
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CS0: OutputPin,
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CS1: OutputPin,
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CS2: OutputPin,
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GPIO: OutputPin,
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{
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type Error = Error<E>;
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fn select_chip(&mut self, chip: u8) -> Result<(), Self::Error> {
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@ -77,17 +80,38 @@ where
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}
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}
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pub trait DoOnGetRefMutData<SPI, CS0, CS1, CS2> {
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trait IssueIOUpdate {
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type Error;
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fn issue_io_update(&mut self) -> Result<(), Self::Error>;
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}
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impl<SPI, CS0, CS1, CS2, GPIO, E> IssueIOUpdate for CPLDData<SPI, CS0, CS1, CS2, GPIO>
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where
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SPI: Transfer<u8>,
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CS0: OutputPin,
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CS1: OutputPin,
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CS2: OutputPin,
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GPIO: OutputPin<Error = E>,
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{
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type Error = Error<E>;
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fn issue_io_update(&mut self) -> Result<(), Self::Error> {
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self.io_update.set_high().map_err(|_| Error::IOUpdateError)?;
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self.io_update.set_low().map_err(|_| Error::IOUpdateError)
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}
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}
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pub trait DoOnGetRefMutData<SPI, CS0, CS1, CS2, GPIO> {
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fn do_on_get_ref_mut_data<R, E>(
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&self,
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f: impl FnOnce(cell::RefMut<CPLDData<SPI, CS0, CS1, CS2>>) -> Result<R, Error<E>>,
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f: impl FnOnce(cell::RefMut<CPLDData<SPI, CS0, CS1, CS2, GPIO>>) -> Result<R, Error<E>>,
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) -> Result<R, Error<E>>;
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}
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impl<SPI, CS0, CS1, CS2> DoOnGetRefMutData<SPI, CS0, CS1, CS2> for CPLD<SPI, CS0, CS1, CS2> {
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impl<SPI, CS0, CS1, CS2, GPIO> DoOnGetRefMutData<SPI, CS0, CS1, CS2, GPIO> for CPLD<SPI, CS0, CS1, CS2, GPIO> {
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fn do_on_get_ref_mut_data<R, E>(
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&self,
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f: impl FnOnce(cell::RefMut<CPLDData<SPI, CS0, CS1, CS2>>) -> Result<R, Error<E>>,
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f: impl FnOnce(cell::RefMut<CPLDData<SPI, CS0, CS1, CS2, GPIO>>) -> Result<R, Error<E>>,
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) -> Result<R, Error<E>> {
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let dev = self
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.data
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@ -97,12 +121,13 @@ impl<SPI, CS0, CS1, CS2> DoOnGetRefMutData<SPI, CS0, CS1, CS2> for CPLD<SPI, CS0
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}
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}
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impl<SPI, CS0, CS1, CS2, E> Transfer<u8> for CPLD<SPI, CS0, CS1, CS2>
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impl<SPI, CS0, CS1, CS2, GPIO, E> Transfer<u8> for CPLD<SPI, CS0, CS1, CS2, GPIO>
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where
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SPI: Transfer<u8, Error = E>,
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CS0: OutputPin,
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CS1: OutputPin,
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CS2: OutputPin,
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GPIO: OutputPin,
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{
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type Error = Error<E>;
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@ -111,19 +136,21 @@ where
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}
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}
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impl<SPI, CS0, CS1, CS2, E> CPLD<SPI, CS0, CS1, CS2> where
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impl<SPI, CS0, CS1, CS2, GPIO, E> CPLD<SPI, CS0, CS1, CS2, GPIO> where
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SPI: Transfer<u8, Error = E>,
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CS0: OutputPin,
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CS1: OutputPin,
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CS2: OutputPin,
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GPIO: OutputPin
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{
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// Constructor for CPLD
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pub fn new(spi: SPI, chip_select: (CS0, CS1, CS2)) -> Self {
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pub fn new(spi: SPI, chip_select: (CS0, CS1, CS2), io_update: GPIO) -> Self {
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// Init data
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let data = CPLDData {
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spi,
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chip_select,
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io_update,
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};
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// Init CPLD
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@ -133,13 +160,13 @@ impl<SPI, CS0, CS1, CS2, E> CPLD<SPI, CS0, CS1, CS2> where
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}
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// Destroy the wrapper, return the CPLD data
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pub fn destroy(self) -> (SPI, (CS0, CS1, CS2)) {
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pub fn destroy(self) -> (SPI, (CS0, CS1, CS2), GPIO) {
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let cpld = self.data.into_inner();
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(cpld.spi, cpld.chip_select)
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(cpld.spi, cpld.chip_select, cpld.io_update)
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}
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// Split SPI into chips, wrapped by Parts struct
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pub fn split<'a>(&'a self) -> Parts<'a, CPLD<SPI, CS0, CS1, CS2>, SPI, CS0, CS1, CS2> {
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pub fn split<'a>(&'a self) -> Parts<'a, CPLD<SPI, CS0, CS1, CS2, GPIO>, SPI, CS0, CS1, CS2, GPIO> {
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Parts::new(&self)
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}
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@ -148,3 +175,18 @@ impl<SPI, CS0, CS1, CS2, E> CPLD<SPI, CS0, CS1, CS2> where
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self.do_on_get_ref_mut_data(|mut dev| dev.select_chip(channel))
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}
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}
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impl<SPI, CS0, CS1, CS2, GPIO, E> CPLD<SPI, CS0, CS1, CS2, GPIO>
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where
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SPI: Transfer<u8>,
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CS0: OutputPin,
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CS1: OutputPin,
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CS2: OutputPin,
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GPIO: OutputPin<Error = E>
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{
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// Issue I/O Update
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pub fn issue_io_update(&mut self) -> Result<(), Error<E>> {
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self.do_on_get_ref_mut_data(|mut dev| dev.issue_io_update())
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}
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}
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135
src/main.rs
135
src/main.rs
@ -75,7 +75,7 @@ fn main() -> ! {
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let miso = gpioa.pa6.into_alternate_af5();
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let (mut cs0, mut cs1, mut cs2) = (
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let (cs0, cs1, cs2) = (
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gpiob.pb12.into_push_pull_output(),
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gpioa.pa15.into_push_pull_output(),
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gpioc.pc7.into_push_pull_output(),
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@ -84,37 +84,83 @@ fn main() -> ! {
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/*
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* I/O_Update -> PB13
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*/
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// TODO: Incoporate io_update into DDS
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let mut io_update = gpiob.pb15.into_push_pull_output();
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let mut spi = dp.SPI1.spi(
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let spi = dp.SPI1.spi(
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(sclk, miso, mosi),
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spi::MODE_0,
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3.mhz(),
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ccdr.peripheral.SPI1,
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&ccdr.clocks,
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);
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// debug led
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let mut yellow = gpioe.pe1.into_push_pull_output();
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yellow.set_high().unwrap();
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/*
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let mut switch = CPLD::new(spi, (cs0, cs1, cs2));
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let mut switch = CPLD::new(spi, (cs0, cs1, cs2), io_update);
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let parts = switch.split();
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let mut config = ConfigRegister::new(parts.spi1);
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let mut att = Attenuator::new(parts.spi2);
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let mut dds0 = DDS::new(parts.spi4);
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loop {
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let mut counter = config.get_status(StatusMask::RF_SW).unwrap();
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hprintln!("{}", counter);
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config.set_configurations(&mut [
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(CFGMask::RF_SW, ((counter + 1)%16) as u32)
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]).unwrap();
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}
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*/
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// Reset all DDS, set CLK_SEL to 0
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config.set_configurations(&mut [
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(CFGMask::RST, 1),
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(CFGMask::IO_RST, 1),
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(CFGMask::IO_UPDATE, 0)
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]).unwrap();
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config.set_configurations(&mut [
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(CFGMask::IO_RST, 0),
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(CFGMask::RST, 0),
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(CFGMask::RF_SW, 1)
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]).unwrap();
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dds0.write_register(0x00, &mut[
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0x00, 0x00, 0x00, 0x02
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]).unwrap();
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// io_update.set_high().unwrap();
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// io_update.set_low().unwrap();
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// switch.issue_io_update();
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dds0.write_register(0x02, &mut[
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0x01F, 0x3F, 0xC0, 0x00
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]).unwrap();
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// io_update.set_high().unwrap();
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// io_update.set_low().unwrap();
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// switch.issue_io_update();
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hprintln!("{:#X?}", dds0.read_register(0x00, &mut[
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0x00, 0x00, 0x00, 0x00
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]).unwrap()).unwrap();
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// Calculate FTW
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let f_out = 10_000_000;
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let f_sclk = 100_000_000;
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let resolution :u64 = 1 << 32;
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let ftw = (resolution * f_out / f_sclk) as u32;
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hprintln!("{}", ftw);
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// Read single-tone profile 0
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let mut profile :[u8; 8] = [0; 8];
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dds0.read_register(0x0E, &mut profile).unwrap();
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// Overwrite FTW on profile
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profile[4] = ((ftw >> 24) & 0xFF) as u8;
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profile[5] = ((ftw >> 16) & 0xFF) as u8;
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profile[6] = ((ftw >> 8 ) & 0xFF) as u8;
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profile[7] = ((ftw >> 0 ) & 0xFF) as u8;
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dds0.write_register(0x0E, &mut profile).unwrap();
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// io_update.set_high().unwrap();
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// io_update.set_low().unwrap();
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// switch.issue_io_update();
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hprintln!("{:#X?}", dds0.read_register(0x0E, &mut profile).unwrap()).unwrap();
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/*
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cs0.set_low().unwrap();
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cs1.set_low().unwrap();
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cs2.set_low().unwrap();
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@ -139,29 +185,72 @@ fn main() -> ! {
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cs0.set_low().unwrap();
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// Release reset, control I/O Update through EEM
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// Relay clock signal from internal OSC (CLK_SEL = 0)
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// Enable Switch 0
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cs0.set_high().unwrap();
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spi.transfer(&mut [
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0x00, 0x00, 0x0A
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0x00, 0x00, 0x01
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]).unwrap();
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cs0.set_low().unwrap();
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cs0.set_low().unwrap();
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cs1.set_low().unwrap();
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cs2.set_high().unwrap();
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hprintln!("{:?}", spi.transfer(&mut [
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// Configure SDIO to be input only, enable 3-wires communication
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spi.transfer(&mut [
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0x00, 0x00, 0x00, 0x00, 0x02
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]).unwrap()).unwrap();
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]).unwrap();
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// IO Update after every SPI transfer
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io_update.set_high().unwrap();
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delay.delay_ms(1_u16);
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io_update.set_low().unwrap();
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// Bypass PLL, bypass divisor
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spi.transfer(&mut [
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0x02, 0x1F, 0x3F, 0xC0, 0x00
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]).unwrap();
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io_update.set_high().unwrap();
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delay.delay_ms(1_u16);
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io_update.set_low().unwrap();
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hprintln!("{:?}", spi.transfer(&mut [
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0x80, 0x00, 0x00, 0x00, 0x00
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hprintln!("{:#X?}", spi.transfer(&mut [
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0x82, 0x00, 0x00, 0x00, 0x00
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]).unwrap()).unwrap();
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let f_out = 10_000_000.0;
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let f_sclk = 100_000_000.0;
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let resolution :u64 = 1 << 32;
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let ftw = ((resolution as f32) * f_out / f_sclk) as u32;
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hprintln!("{:#X}", ftw);
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// Read profile 0
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let mut profile_arr_0 :[u8; 9] = [0; 9];
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profile_arr_0[0] = 0x8E;
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hprintln!("{:#X?}", spi.transfer(&mut profile_arr_0).unwrap()).unwrap();
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// Write FTW to profile 0
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profile_arr_0[0] = 0x0E;
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profile_arr_0[5] = ((ftw >> 24) & 0xFF) as u8;
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profile_arr_0[6] = ((ftw >> 16) & 0xFF) as u8;
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profile_arr_0[7] = ((ftw >> 8 ) & 0xFF) as u8;
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profile_arr_0[8] = ((ftw >> 0 ) & 0xFF) as u8;
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hprintln!("{:#X?}", profile_arr_0).unwrap();
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spi.transfer(&mut profile_arr_0).unwrap();
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// Update after write
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io_update.set_high().unwrap();
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delay.delay_ms(1_u16);
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io_update.set_low().unwrap();
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// Read profile again, new value should be present
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profile_arr_0[0] = 0x8E;
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hprintln!("{:#X?}", spi.transfer(&mut profile_arr_0).unwrap()).unwrap();
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*/
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loop {}
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}
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@ -4,45 +4,47 @@ use embedded_hal::{
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};
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use core::marker::PhantomData;
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use crate::{DoOnGetRefMutData, Error, SelectChip};
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use crate::{DoOnGetRefMutData, Error, SelectChip, IssueIOUpdate};
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pub struct SPISlave<'a, DEV: 'a, SPI, CS0, CS1, CS2> (
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pub struct SPISlave<'a, DEV: 'a, SPI, CS0, CS1, CS2, GPIO> (
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&'a DEV,
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u8,
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PhantomData<(SPI, CS0, CS1, CS2)>,
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u8, // Channel of SPI slave
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bool, // Need I/O Update
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PhantomData<(SPI, CS0, CS1, CS2, GPIO)>,
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);
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pub struct Parts<'a, DEV: 'a, SPI, CS0, CS1, CS2> {
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pub spi1: SPISlave<'a, DEV, SPI, CS0, CS1, CS2>,
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pub spi2: SPISlave<'a, DEV, SPI, CS0, CS1, CS2>,
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pub spi3: SPISlave<'a, DEV, SPI, CS0, CS1, CS2>,
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pub spi4: SPISlave<'a, DEV, SPI, CS0, CS1, CS2>,
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pub spi5: SPISlave<'a, DEV, SPI, CS0, CS1, CS2>,
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pub spi6: SPISlave<'a, DEV, SPI, CS0, CS1, CS2>,
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pub spi7: SPISlave<'a, DEV, SPI, CS0, CS1, CS2>,
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pub struct Parts<'a, DEV: 'a, SPI, CS0, CS1, CS2, GPIO> {
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pub spi1: SPISlave<'a, DEV, SPI, CS0, CS1, CS2, GPIO>,
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pub spi2: SPISlave<'a, DEV, SPI, CS0, CS1, CS2, GPIO>,
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pub spi3: SPISlave<'a, DEV, SPI, CS0, CS1, CS2, GPIO>,
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pub spi4: SPISlave<'a, DEV, SPI, CS0, CS1, CS2, GPIO>,
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pub spi5: SPISlave<'a, DEV, SPI, CS0, CS1, CS2, GPIO>,
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pub spi6: SPISlave<'a, DEV, SPI, CS0, CS1, CS2, GPIO>,
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pub spi7: SPISlave<'a, DEV, SPI, CS0, CS1, CS2, GPIO>,
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}
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impl<'a, DEV, SPI, CS0, CS1, CS2> Parts<'a, DEV, SPI, CS0, CS1, CS2> {
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impl<'a, DEV, SPI, CS0, CS1, CS2, GPIO> Parts<'a, DEV, SPI, CS0, CS1, CS2, GPIO> {
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pub(crate) fn new(cpld: &'a DEV) -> Self {
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Parts {
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spi1: SPISlave(&cpld, 1, PhantomData),
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spi2: SPISlave(&cpld, 2, PhantomData),
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spi3: SPISlave(&cpld, 3, PhantomData),
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spi4: SPISlave(&cpld, 4, PhantomData),
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spi5: SPISlave(&cpld, 5, PhantomData),
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spi6: SPISlave(&cpld, 6, PhantomData),
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spi7: SPISlave(&cpld, 7, PhantomData),
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spi1: SPISlave(&cpld, 1, false, PhantomData),
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spi2: SPISlave(&cpld, 2, false, PhantomData),
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spi3: SPISlave(&cpld, 3, true, PhantomData),
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spi4: SPISlave(&cpld, 4, true, PhantomData),
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spi5: SPISlave(&cpld, 5, true, PhantomData),
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spi6: SPISlave(&cpld, 6, true, PhantomData),
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spi7: SPISlave(&cpld, 7, true, PhantomData),
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}
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}
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}
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|
||||
impl<'a, DEV, SPI, CS0, CS1, CS2, E> Transfer<u8> for SPISlave<'a, DEV, SPI, CS0, CS1, CS2>
|
||||
impl<'a, DEV, SPI, CS0, CS1, CS2, GPIO, E> Transfer<u8> for SPISlave<'a, DEV, SPI, CS0, CS1, CS2, GPIO>
|
||||
where
|
||||
CS2: OutputPin,
|
||||
CS1: OutputPin,
|
||||
CS0: OutputPin,
|
||||
DEV: DoOnGetRefMutData<SPI, CS0, CS1, CS2>,
|
||||
DEV: DoOnGetRefMutData<SPI, CS0, CS1, CS2, GPIO>,
|
||||
SPI: Transfer<u8, Error = E>,
|
||||
GPIO: OutputPin,
|
||||
{
|
||||
type Error = Error<E>;
|
||||
|
||||
@ -51,6 +53,9 @@ where
|
||||
dev.select_chip(self.1);
|
||||
let result = dev.spi.transfer(words).map_err(Error::SPI);
|
||||
dev.select_chip(0);
|
||||
if self.2 {
|
||||
dev.issue_io_update();
|
||||
}
|
||||
result
|
||||
})
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user