forked from M-Labs/humpback-dds
nmigen: purged
This commit is contained in:
parent
00938bcb23
commit
14aab2d040
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@ -1,43 +0,0 @@
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# If the design does not create a "sync" clock domain, it is created by the nMigen build system
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# using the platform default clock (and default reset, if any).
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from nmigen import *
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from humpback import *
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#class SimpleBlinky(Elaboratable):
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# def elaborate(self, platform):
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# led = platform.request("user_led", 0)
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# counter = Signal(24)
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# m = Module()
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# m.d.sync += counter.eq(counter + 1)
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# m.d.comb += led.o.eq(counter[23])
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# return m
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# Simple connector from STM32 SPI to Humpback SPI
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class UrukulConnector(Elaboratable):
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def elaborate(self, platform):
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# Acquire SPI slave, EEM port 1 output
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spi = platform.request("spi")
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print(spi)
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eem = platform.request("eem", 1)
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print(eem)
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clk25 = platform.request("clk25")
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counter = Signal(25)
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m = Module()
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m.domains.sync = ClockDomain()
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m.d.comb += ClockSignal().eq(clk25.i)
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m.d.sync += counter.eq(counter + 1)
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return m
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if __name__ == "__main__":
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platform = HumpbackPlatform()
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platform.add_resources(platform.eem_to_urukul)
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platform.add_resources(platform.spi)
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platform.build(UrukulConnector(), do_program=False)
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@ -1,339 +0,0 @@
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# Strongly inspired by the migen build of humpback
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# Using STM32 Nucleo-H743ZI2 board
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# Note to self: Pin assignment differs from Nucleo-H743ZI
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import os
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import subprocess
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from nmigen.build import *
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from nmigen.vendor.lattice_ice40 import *
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from nmigen_boards.resources import *
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from resources import *
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__all__ = ["HumpbackPlatform"]
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class HumpbackPlatform(LatticeICE40Platform):
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device = "iCE40HX8K" # Using ICE40HX8K-CT256
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package = "CT256"
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default_clk = "clk25"
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resources = [
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# Define clock
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Resource("clk25", 0, Pins("K9", dir="i"),
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Clock(25e6), Attrs(GLOBAL=True, IO_STANDARD="SB_LVCMOS")
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),
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# Define user LED
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Resource("user_led", 0, Pins("H3", dir="o"),
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Attrs(IO_STANDARD="SB_LVCMOS")
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),
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# TODO: Define UART interfaces somewhere else, make it optional
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UARTResource(0,
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rx="T11", tx="M13", rts="M15", cts="T10",
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attrs=Attrs(IO_STANDARD="SB_LVCMOS", PULLUP=1)
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),
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# UART1 interface: Read note for UART interface above
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# UART1 interface is broken due to pin rearrangement introduced for Nucleo-H743ZI2
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# Uncomment if fixed, or found an alternative (e.g. bit banging UART)
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# *UARTResource(1,
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# tx="M11", rx="T13", rts="A6", cts="B16",
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# attrs=Attrs(IO_STANDARD="SB_LVCMOS", PULLUP=1)
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# ),
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# Define I2C interface
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# TODO: Make it optional, declare it in a block itself
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# Use "role=device" to make humpback a I2C slave
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I2CResource(0,
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sda="T16", scl="M12",
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attrs=Attrs(IO_STANDARD="SB_LVCMOS", PULLUP=1)
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),
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]
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# Using the dict approach in (o)migen
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connectors = [
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# EEM0 Connector
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Connector("eem", 0, {
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"d0_cc_n": "H1",
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"d0_cc_p": "J3",
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"d1_n" : "B1",
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"d1_p" : "F5",
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"d2_n" : "C2",
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"d2_p" : "C1",
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"d3_n" : "D2",
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"d3_p" : "F4",
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"d4_n" : "D1",
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"d4_p" : "G5",
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"d5_n" : "E3",
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"d5_p" : "G4",
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"d6_n" : "E2",
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"d6_p" : "H5",
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"d7_n" : "F3",
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"d7_p" : "G3",
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}),
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# EEM1 Connector
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Connector("eem", 1, {
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"d0_cc_n": "L3",
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"d0_cc_p": "L6",
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"d1_n" : "F1",
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"d1_p" : "H6",
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"d2_n" : "G2",
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"d2_p" : "H4",
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"d3_n" : "H2",
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"d3_p" : "J4",
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"d4_n" : "J1",
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"d4_p" : "J2",
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"d5_n" : "K3",
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"d5_p" : "K1",
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"d6_n" : "L1",
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"d6_p" : "L4",
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"d7_n" : "M1",
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"d7_p" : "K4",
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}),
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# EEM2 Connector
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Connector("eem", 2, {
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"d0_cc_n": "G1",
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"d0_cc_p": "J5",
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"d1_n" : "M2",
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"d1_p" : "K5",
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"d2_n" : "N2",
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"d2_p" : "L7",
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"d3_n" : "M3",
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"d3_p" : "M6",
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"d4_n" : "N3",
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"d4_p" : "L5",
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"d5_n" : "M4",
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"d5_p" : "P1",
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"d6_n" : "M5",
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"d6_p" : "P2",
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"d7_n" : "N4",
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"d7_p" : "R1",
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}),
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# STM32 Nucleo/ Arduino Connector
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# TODO: Suspect SPI mismatch forever
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Connector("stm32", 0, {
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"PA0": "A2",
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# "PA1": "P14", # PA1 -> PB2, but PB2 has a mapping on FPGA already
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# "PA2": "B8", # PA2 -> PF6
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"PA3": "L13",
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"PA5": "C8",
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"PA6": "T2",
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# "PA7": "N12", # PA7 -> PE9, but PE9 has a mapping on FPGA already
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# "PA8": "M9", # PA8 -> PF2
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# "PA9": "P10", # PA9 -> PF1
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# "PA10": "R10", # PA10 -> PF0
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"PA15": "B14",
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"PB0": "A1",
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# "PB1": "G12", # PB1 -> PF4
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"PB1": "M14", # PC1 -> PB1
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"PB2": "B6",
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"PB5": "N5",
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# "PB6": "A7", # PB6 -> PG6
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"PB6": "T13", # PG9 -> PB6
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"PB7": "M11", # PG10 -> PB7
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"PB8": "M12",
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"PB9": "T16",
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"PB10": "C3",
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"PB11": "F7",
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"PB12": "B13",
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"PB13": "B12",
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"PB15": "A11",
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"PC0": "L14",
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# "PC1": "M14", # PC1 -> PB1
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# "PC2": "A9", # PC2 -> PF5
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"PC2": "N16", # PC4 -> PC2
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"PC3": "M16",
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# "PC4": "N16", # PC4 -> PC2
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# "PC5": "P16", # PC5 -> PF10
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"PC6": "B10",
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"PC7": "B15",
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"PC8": "H16",
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"PC9": "J10",
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"PC10": "J16",
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"PC11": "J15",
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"PC12": "K12",
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"PD0": "T9",
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"PD1": "N9",
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"PD2": "K13",
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"PD3": "T10",
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"PD4": "A6",
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"PD5": "T11",
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"PD6": "M13",
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"PD7": "L12",
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"PD11": "E5",
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"PD12": "D5",
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"PD13": "C5",
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"PD14": "R2",
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"PE0": "D3",
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"PE2": "P15",
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"PE3": "N10",
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"PE4": "R15",
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"PE5": "T15",
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"PE6": "M8",
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"PE7": "E6",
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"PE8": "D6",
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"PE9": "F12",
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"PE10": "A5",
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"PE11": "G11",
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"PE12": "B4",
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# "PE13": "F11", # PE13 -> PG12
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# "PE14": "C4", # PE14 -> PE6, but PE6 has a mapping on FPGA already
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"PE14": "B9", # PF14 -> PE14
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"PE15": "B3",
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"PF0": "R10", # PA10 -> PF0
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"PF1": "P10", # PA9 -> PF1
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"PF2": "M9", # PA8 -> PF2
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"PF4": "G12", # PB1 -> PF4
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"PF5": "A9", # PC2 -> PF5
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"PF6": "B8", # PA2 -> PF6
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"PF7": "L9",
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"PF8": "L10",
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"PF9": "P9",
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"PF10": "P16", # PC5 -> PF10
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# "PF14": "B9", # PF14 -> PE14
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# "PF15": "B16", # PF15 -> PG14
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"PG0": "M7",
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"PG1": "P8",
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"PG2": "K14",
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"PG3": "K15",
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"PG6": "A7", # PB6 -> PG6
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# "PG9": "T13", # PG9 -> PB6
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# "PG10": "M11", # PG10 -> PB7
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"PG12": "F11", # PE13 -> PG12
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"PG14": "B16", # PF15 -> PG14
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}),
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# Beaglebone Black Connector
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Connector("bb", 0, {
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"CLKOUT": "R9",
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"GPIO0_7": "R14",
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"GPIO1_16": "A16",
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"GPIO1_17": "R3",
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"GPIO1_29": "D11",
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"GPIO1_31": "D14",
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"GPIO2_6": "D16",
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"GPIO2_7": "C16",
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"GPIO2_8": "E16",
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"GPIO2_9": "D15",
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"GPIO2_11": "F15",
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"GPIO2_13": "F16",
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"GPIO2_22": "C11",
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"GPIO2_23": "C10",
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"GPIO2_24": "E10",
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"GPIO2_25": "D4",
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"GPIO3_19": "P4",
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"GPIO3_21": "R4",
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"GPMC_A2": "T7",
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"GPMC_A3": "T1",
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"GPMC_A14": "F9",
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"GPMC_A15": "B7",
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"GPMC_AD0": "C12",
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"GPMC_AD1": "E11",
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"GPMC_AD2": "J12",
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"GPMC_AD3": "J11",
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"GPMC_AD4": "C13",
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"GPMC_AD5": "C14",
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"GPMC_AD6": "J14",
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"GPMC_AD7": "J13",
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"GPMC_AD8": "E13",
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"GPMC_AD9": "G13",
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"GPMC_AD10": "G14",
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"GPMC_AD11": "G10",
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"GPMC_AD12": "E14",
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"GPMC_AD13": "H14",
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"GPMC_AD14": "F14",
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"GPMC_AD15": "F13",
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"GPMC_ADVN": "H12",
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"GPMC_BE0N": "G16",
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"GPMC_CLK": "H11",
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"GPMC_CSN1": "D13",
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"GPMC_OEN": "H13",
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"GPMC_WE1N": "G15",
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}),
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# ESP32 Connector
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Connector("esp32", 0, {
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"IO2": "D9",
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"IO4": "D7",
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"IO22": "C7",
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"IO34": "E9",
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"IO35": "C9",
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}),
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# OrangePI Zero Connector
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Connector("orange_pi", 0, {
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"PG06": "A15",
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}),
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]
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# Half completed, second EEM resource to be added
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# Appears that DiffPairs cause build problem
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# eem_to_urukul_diffpairs = [
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# Resource("eem", 1,
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# Subsignal("sclk", DiffPairs("L6", "L3", dir="o")),
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# Subsignal("mosi", DiffPairs("H6", "F1", dir="o")),
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# Subsignal("miso", DiffPairs("H4", "G2", dir="i"),
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# Attrs(IO_STANDARD="SB_LVDS_INPUT")),
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# Subsignal("cs", DiffPairs("K1 J2 J4", "K3 J1 H2", dir="o")),
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# Subsignal("io_update", DiffPairs("L4", "L1", dir="o")),
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# Subsignal("sync_out", DiffPairs("K4", "M1", dir="o")),
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# Attrs(IO_STANDARD="SB_LVCMOS")
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# )
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# ]
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eem_to_urukul = [
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Resource("eem", 1,
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Subsignal("sclk_p", Pins("L6", dir="o"), Attrs(IO_STANDARD="SB_LVCMOS")),
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Subsignal("sclk_n", Pins("L3", dir="o"), Attrs(IO_STANDARD="SB_LVCMOS")),
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# Subsignal("sclk", DiffPairs("L6", "L3", dir="o"), Attrs(IO_STANDARD="SB_LVCMOS")),
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Subsignal("mosi_p", Pins("H6", dir="o"), Attrs(IO_STANDARD="SB_LVCMOS")),
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Subsignal("mosi_n", Pins("F1", dir="o"), Attrs(IO_STANDARD="SB_LVCMOS")),
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# Subsignal("miso_p", Pins("H4", dir="i"), Attrs(IO_STANDARD="SB_IDK")),
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# Subsignal("miso_n", Pins("G2", dir="i"), Attrs(IO_STANDARD="SB_LOL")),
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Subsignal("miso", DiffPairs("H4", "G2", dir="i"), Attrs(IO_STANDARD="SB_LVDS_INPUT")),
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Subsignal("cs_p", Pins("J4 J2 K1", dir="o"), Attrs(IO_STANDARD="SB_LVCMOS")),
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Subsignal("cs_n", Pins("H2 J1 K3", dir="o"), Attrs(IO_STANDARD="SB_LVCMOS")),
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Subsignal("io_update_p", Pins("L4", dir="o"), Attrs(IO_STANDARD="SB_LVCMOS")),
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Subsignal("io_update_n", Pins("L1", dir="o"), Attrs(IO_STANDARD="SB_LVCMOS")),
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Subsignal("sync_out_p", Pins("K4", dir="o"), Attrs(IO_STANDARD="SB_LVCMOS")),
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Subsignal("sync_out_n", Pins("M1", dir="o"), Attrs(IO_STANDARD="SB_LVCMOS")),
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),
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]
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# SPI Connection to Urukul, using (PD14, PA15, PC7) as connection pins
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spi = [
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Resource("spi", 0,
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Subsignal("cs", Pins("R2 B14 B15", dir="i")),
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Subsignal("mosi", Pins("N5", dir="i")),
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Subsignal("miso", Pins("T2", dir="oe")),
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Subsignal("sck", Pins("C8", dir="i"),
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Attrs(GLOBAL=True)),
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Attrs(IO_STANDARD="SB_LVCMOS")
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)
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]
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# tool chain setup, using default ICE40 HX8K evaluation code
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def toolchain_program(self, products, name):
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iceprog = os.environ.get("ICEPROG", "iceprog")
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with products.extract("{}.bin".format(name)) as bitstream_filename:
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subprocess.check_call([iceprog, "-S", bitstream_filename])
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@ -1,90 +0,0 @@
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from nmigen.build import *
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__all__ = ["I2CResource"]
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def I2CResource(*args, sda, scl, conn=None, attrs=None, role="host"):
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assert role in ("host", "device")
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io = []
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# sda line: I/O port for the data line
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io.append(Subsignal("sda", Pins(sda, dir="io", conn=conn, assert_width=1)))
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# sck line: I2C clock signal outputs from master to slave
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if role == "host":
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io.append(Subsignal("scl", Pins(scl, dir="o", conn=conn, assert_width=1)))
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else: #device
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io.append(Subsignal("scl", Pins(scl, dir="i", conn=conn, assert_width=1)))
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if attrs is not None:
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io.append(attrs)
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return Resource.family(*args, default_name="i2c", ios=io)
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'''
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# Auto create a resource list given a set of iCE40 pins and STM32 pin names (pins_dict)
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def GPIOResources(*args, pins_dict, dir = "o", invert=False, conn=None, attrs=None):
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# Check data integrity: pins_dict must be a dict AND port must be from a to k
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assert isinstance(pins_dict, dict)
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# Debug: dir == "o"
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assert dir == "o"
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# List of resources to be returned
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resources = []
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for STM32_pin, iCE40_pin in pins_dict.items():
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# Set all gpio pins to be output only for the time being
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# TODO: Allow dir argument.
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ios = [Pins(iCE40_pin, dir=dir, invert=invert, conn=conn)]
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if attrs is not None:
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ios.append(attrs)
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# Extract GPIO port and port number from STM32_pin
|
||||
# Strip "P" from P<port><port_num>
|
||||
if STM32_pin.startswith('P'):
|
||||
STM32_pin = STM32_pin[1:]
|
||||
|
||||
# Acquire port from <port><port_num>
|
||||
port = STM32_pin[0].lower()
|
||||
port_num = int(STM32_pin[1:])
|
||||
|
||||
# Insert gpio<port>.<portNum> into resources list
|
||||
resources.append(Resource.family(*args, port_num, default_name=("gpio"+port), ios=ios))
|
||||
return resources
|
||||
|
||||
# Auto create a resource list for differential I/O
|
||||
def DiffResources(*args, eem_pins, invert=False, conn=None, attrs=None, dir):
|
||||
# TODO: Everything
|
||||
|
||||
# assert dimensionality
|
||||
assert isinstance(eem_pins, list)
|
||||
assert isinstance(eem_pins[0], list)
|
||||
assert isinstance(eem_pins[0][0], list)
|
||||
assert isinstance(eem_pins[0][0][0], str)
|
||||
|
||||
# assert direction to be either input or output
|
||||
# reject tristate or bidirectional pin
|
||||
assert dir in ("i", "o")
|
||||
|
||||
|
||||
|
||||
|
||||
if __name__ == "__main__":
|
||||
|
||||
from pin_mapper import *
|
||||
eem = diffMapping()
|
||||
DiffResources(eem_pins = eem, dir = "o",
|
||||
attrs=Attrs(IO_STANDARD="SB_LVCMOS")
|
||||
)
|
||||
'''
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
19
shell.nix
19
shell.nix
|
|
@ -4,9 +4,6 @@ let
|
|||
in with pkgs;
|
||||
let
|
||||
migen = callPackage ./nix/migen.nix {};
|
||||
# nMigen support for DiffPairs and IO_STANDARD="SB_LVDS_INPUT" seems questionable
|
||||
nmigen = callPackage ./nix/nmigen.nix {};
|
||||
nmigen-boards = callPackage ./nix/nmigen-boards.nix { inherit nmigen; };
|
||||
openocd = callPackage ./nix/openocd.nix {};
|
||||
rustPlatform = callPackage ./nix/rustPlatform.nix {};
|
||||
itm = callPackage ./nix/itm.nix {inherit rustPlatform;};
|
||||
|
|
@ -37,12 +34,12 @@ let
|
|||
set-gdb-config-file && cargo run --example ethernet
|
||||
'';
|
||||
|
||||
editNMigenScript = writeShellScriptBin "edit-nmigen-script" ''
|
||||
nano -m nmigen/fpga_config.py
|
||||
editMigenScript = writeShellScriptBin "edit-migen-script" ''
|
||||
nano -m migen/fpga_config.py
|
||||
'';
|
||||
|
||||
compileNMigenScript = writeShellScriptBin "compile-nmigen-script" ''
|
||||
python3 nmigen/fpga_config.py
|
||||
compileMigenScript = writeShellScriptBin "compile-migen-script" ''
|
||||
python3 migen/fpga_config.py
|
||||
echo "Compiled fpga_config.py to top.bin"
|
||||
'';
|
||||
|
||||
|
|
@ -52,7 +49,7 @@ let
|
|||
|
||||
configureFPGA = writeShellScriptBin "configure-fpga" ''
|
||||
nc -zv localhost 3333 \
|
||||
&& compile-nmigen-script \
|
||||
&& compile-migen-script \
|
||||
&& flash-fpga-config \
|
||||
|| echo "Please run OpenOcd first."
|
||||
'';
|
||||
|
|
@ -72,7 +69,7 @@ in
|
|||
stdenv.mkDerivation {
|
||||
name = "nix-shell";
|
||||
buildInputs = with rustPlatform.rust; [
|
||||
(pkgs.python3.withPackages(ps: [ migen nmigen nmigen-boards]))
|
||||
(pkgs.python3.withPackages(ps: [ migen ]))
|
||||
pkgs.yosys
|
||||
pkgs.nextpnr
|
||||
pkgs.icestorm
|
||||
|
|
@ -85,8 +82,8 @@ in
|
|||
runOpenOcdBlock
|
||||
setGDBConfigFile
|
||||
runEthernetServer
|
||||
editNMigenScript
|
||||
compileNMigenScript
|
||||
editMigenScript
|
||||
compileMigenScript
|
||||
flashFPGAConfig
|
||||
configureFPGA
|
||||
verifyFPGAConfig
|
||||
|
|
|
|||
Loading…
Reference in New Issue