mwojcik
/
datasheets
forked from sinara-hw/datasheets
1
0
Fork 0
Code Pull Requests Activity
147 Commits 3 Branches 0 Tags 8 MiB
Commit Graph

23 Commits

Author SHA1 Message Date
occheung b476c178d0 2118-2128: add min pulse width spec 
Especially test reuslt that validate the "minimum 3ns pulse width" claim.
 2022-02-08 13:33:55 +08:00
occheung 3ed6a7ccbe 2118-2128: fix data rate spec 
Quoted from the isolator datasheet: "Data rates up to 150 Mbps are supported."
Saying the maximum data rate is at least 150 Mbps is not very accurate.
Updates #36
 2022-02-07 14:41:09 +08:00
occheung 1b8beee45d 2118-2128: add max data rate spec 
Base on the isolator datasheet, where it stated that "Data rates up to 150 Mbps are supported".
The electrical specific of the datasheet stated the spec differently.
Updates #36
 2022-02-04 14:38:39 +08:00
occheung 7bdc121b6a 2118-2128: add low input min voltage 
-0.5V from absolute rating
 2022-02-04 14:31:30 +08:00
occheung 0b4ad6762e 2118-2128: add high input max voltage 
5.5V from absolute rating
5V max with termination to respect 0.5W rating of the 50R resistor.
Updates #35
 2022-02-04 14:01:22 +08:00
occheung 47e0c31705 ttl: update direction switches desc 
Updates #33
 2022-02-04 13:30:32 +08:00
occheung 0bdf5d36bc fp pictures: png -> jpg 
re-converted from source with optimization
 2022-01-26 09:57:30 +08:00
occheung 25e441b4ec fp: re-edit & change format to pdf 
Updates #37.
 2022-01-25 14:57:54 +08:00
occheung df9078b897 2118-2128: add BoM manually 
Updates #30.
 2022-01-21 13:01:23 +08:00
occheung 9f6056f615 ttl: remove extra rtio break in example 2022-01-20 14:58:40 +08:00
occheung 9488a03aa4 ttl: factor out examples 
Also, the ttl timestamp_mu method has a parameter.
 2022-01-20 14:51:51 +08:00
occheung 611a0009af bump version 2022-01-19 15:34:54 +08:00
occheung 56082b94c3 2118-2128: add footnote for data source 
Updates #29.
 2022-01-17 14:44:13 +08:00
occheung 4ef628b708 dio: rename transceivers on the IO side 
Naming all transceivers on the IO side as "IO Bus Transceiver(s)".
Just to differentiate it from LVDS transceivers.
Closes #21.
 2022-01-14 14:41:14 +08:00
occheung 3654502d1b dio: add spec sources 
Also remove propagation delay specs from LVDS-TTL.
PCB traces would make a significant impact.
 2022-01-14 14:09:32 +08:00
occheung 7230cdbec1 2118-2128: clarify connector type 
Just to clarify, no self converting mechanical magic here.
Closes #27.
 2022-01-14 13:05:21 +08:00
Sebastien Bourdeauducq cd7d118f7c update disclaimers 2022-01-14 11:55:48 +08:00
occheung 6b24b54f60 ttl: add switch desc section 
Closes #20.
Closes #22.
 2022-01-11 16:56:38 +08:00
occheung 282b7bf244 move drawings in front of ARTIQ examples 
And some additional reformatting.
 2022-01-07 17:25:34 +08:00
occheung 39b10ecbd2 slightly enlarge FP drawings 2022-01-07 10:37:16 +08:00
occheung ffa71dc40c FP dimen -> FP drawings 2022-01-06 17:32:36 +08:00
occheung 02e9cce585 2118-2128: add front panel figures 
Missing BNC-TTL FP drawings.
 2022-01-06 11:46:30 +08:00
occheung a32c43c0b8 2128 -> 2118/2128 2021-12-23 12:56:11 +08:00