13 Commits

Author	SHA1	Message	Date
occheung	9488a03aa4	ttl: factor out examples ... Also, the ttl timestamp_mu method has a parameter.	2022-01-20 14:51:51 +08:00
occheung	611a0009af	bump version	2022-01-19 15:34:54 +08:00
occheung	56082b94c3	2118-2128: add footnote for data source ... Updates #29.	2022-01-17 14:44:13 +08:00
occheung	4ef628b708	dio: rename transceivers on the IO side ... Naming all transceivers on the IO side as "IO Bus Transceiver(s)". Just to differentiate it from LVDS transceivers. Closes #21.	2022-01-14 14:41:14 +08:00
occheung	3654502d1b	dio: add spec sources ... Also remove propagation delay specs from LVDS-TTL. PCB traces would make a significant impact.	2022-01-14 14:09:32 +08:00
occheung	7230cdbec1	2118-2128: clarify connector type ... Just to clarify, no self converting mechanical magic here. Closes #27.	2022-01-14 13:05:21 +08:00
Sebastien Bourdeauducq	cd7d118f7c	update disclaimers	2022-01-14 11:55:48 +08:00
occheung	6b24b54f60	ttl: add switch desc section ... Closes #20. Closes #22.	2022-01-11 16:56:38 +08:00
occheung	282b7bf244	move drawings in front of ARTIQ examples ... And some additional reformatting.	2022-01-07 17:25:34 +08:00
occheung	39b10ecbd2	slightly enlarge FP drawings	2022-01-07 10:37:16 +08:00
occheung	ffa71dc40c	FP dimen -> FP drawings	2022-01-06 17:32:36 +08:00
occheung	02e9cce585	2118-2128: add front panel figures ... Missing BNC-TTL FP drawings.	2022-01-06 11:46:30 +08:00
occheung	a32c43c0b8	2128 -> 2118/2128	2021-12-23 12:56:11 +08:00