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10 Commits

Author SHA1 Message Date
805beeacaf kasli_soc: separate master drtio memory from rest 2024-11-29 16:08:56 +08:00
e1f493f3ca drtio: add InjectionRequest to expects_response 2024-11-26 14:58:24 +08:00
1f5ea41934 flake: update dependencies 2024-11-20 19:58:55 +08:00
7f83d56ef5 cargo fmt 2024-11-20 09:42:49 +08:00
1d431456f4 Fix DWARF parser treating catch blocks as unconditional
Signed-off-by: Jonathan Coates <jonathan.coates@oxionics.com>
2024-11-20 09:32:38 +08:00
b03e380c1e flake: update dependencies 2024-11-20 09:07:00 +08:00
47fc53c4bf drtio_tuple -> drtio_context 2024-11-18 13:13:10 +08:00
42eaecf9e1 remove debug message 2024-11-18 12:19:37 +08:00
beb7e6f994 cargo fmt 2024-11-18 12:19:37 +08:00
4502a47aa6 drtio_proto: add allocate step for flashing
This avoids reallocation while transfering binaries.
2024-11-18 12:19:37 +08:00
8 changed files with 123 additions and 48 deletions

8
flake.lock generated
View File

@ -11,11 +11,11 @@
"src-pythonparser": "src-pythonparser"
},
"locked": {
"lastModified": 1731734344,
"narHash": "sha256-2vLRo9D5wDs5FArpc2pOfuKFrhnqIKjtZos88VJahhc=",
"lastModified": 1732066716,
"narHash": "sha256-krjvt9+RccnAxSEZcFhRpjA2S3CoqE4MSa1JUg421b4=",
"ref": "refs/heads/master",
"rev": "27d54cb8f3a394b4f4adcbb3c2c9160c5bf3df47",
"revCount": 9049,
"rev": "270a417a28b516d36983779a1adb6d33a3c55a4a",
"revCount": 9102,
"type": "git",
"url": "https://github.com/m-labs/artiq.git"
},

View File

@ -8,7 +8,9 @@ from migen.build.generic_platform import *
from migen.genlib.resetsync import AsyncResetSynchronizer
from migen.genlib.cdc import MultiReg
from migen_axi.integration.soc_core import SoCCore
from migen_axi.interconnect import axi, axi2csr
from migen_axi.platforms import kasli_soc
from misoc.interconnect import csr_bus
from misoc.interconnect.csr import *
from misoc.cores import virtual_leds
@ -308,6 +310,14 @@ class GenericMaster(SoCCore):
self.submodules.rtio_tsc = rtio.TSC(glbl_fine_ts_width=3)
self.submodules.drtio_axi2csr = axi2csr.AXI2CSR(
bus_csr=csr_bus.Interface(self.csr_data_width, self.csr_address_width),
bus_axi=axi.Interface.like(self.ps7.m_axi_gp0))
self.register_mem("drtio_csr", self.mem_map["axi"],
4 * 2**(self.csr_address_width),
self.drtio_axi2csr.bus)
self.drtio_csr_group = []
self.drtioaux_csr_group = []
self.drtioaux_memory_group = []
@ -332,9 +342,9 @@ class GenericMaster(SoCCore):
self.csr_devices.append(coreaux_name)
size = coreaux.get_mem_size()
memory_address = self.axi2csr.register_port(coreaux.get_tx_port(), size)
self.axi2csr.register_port(coreaux.get_rx_port(), size)
self.add_memory_region(memory_name, self.mem_map["csr"] + memory_address, size * 2)
memory_address = self.drtio_axi2csr.register_port(coreaux.get_tx_port(), size)
self.drtio_axi2csr.register_port(coreaux.get_rx_port(), size)
self.add_memory_region(memory_name, self.mem_map["axi"] + memory_address, size * 2)
self.config["HAS_DRTIO"] = None
self.config["HAS_DRTIO_ROUTING"] = None

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@ -333,6 +333,10 @@ pub enum Packet {
destination: u8,
},
CoreMgmtFlashRequest {
destination: u8,
payload_length: u32,
},
CoreMgmtFlashAddDataRequest {
destination: u8,
last: bool,
length: u16,
@ -694,24 +698,28 @@ impl Packet {
0xda => Packet::CoreMgmtAllocatorDebugRequest {
destination: reader.read_u8()?,
},
0xdb => {
0xdb => Packet::CoreMgmtFlashRequest {
destination: reader.read_u8()?,
payload_length: reader.read_u32()?,
},
0xdc => {
let destination = reader.read_u8()?;
let last = reader.read_bool()?;
let length = reader.read_u16()?;
let mut data: [u8; MASTER_PAYLOAD_MAX_SIZE] = [0; MASTER_PAYLOAD_MAX_SIZE];
reader.read_exact(&mut data[0..length as usize])?;
Packet::CoreMgmtFlashRequest {
Packet::CoreMgmtFlashAddDataRequest {
destination: destination,
last: last,
length: length,
data: data,
}
}
0xdc => Packet::CoreMgmtDropLinkAck {
0xdd => Packet::CoreMgmtDropLinkAck {
destination: reader.read_u8()?,
},
0xdd => Packet::CoreMgmtDropLink,
0xde => {
0xde => Packet::CoreMgmtDropLink,
0xdf => {
let last = reader.read_bool()?;
let length = reader.read_u16()?;
let mut data: [u8; SAT_PAYLOAD_MAX_SIZE] = [0; SAT_PAYLOAD_MAX_SIZE];
@ -722,7 +730,7 @@ impl Packet {
data: data,
}
}
0xdf => {
0xe0 => {
let last = reader.read_bool()?;
let length = reader.read_u16()?;
let mut value: [u8; SAT_PAYLOAD_MAX_SIZE] = [0; SAT_PAYLOAD_MAX_SIZE];
@ -733,7 +741,7 @@ impl Packet {
value: value,
}
}
0xe0 => Packet::CoreMgmtReply {
0xe1 => Packet::CoreMgmtReply {
succeeded: reader.read_bool()?,
},
@ -1183,36 +1191,44 @@ impl Packet {
writer.write_u8(destination)?;
}
Packet::CoreMgmtFlashRequest {
destination,
payload_length,
} => {
writer.write_u8(0xdb)?;
writer.write_u8(destination)?;
writer.write_u32(payload_length)?;
}
Packet::CoreMgmtFlashAddDataRequest {
destination,
last,
length,
data,
} => {
writer.write_u8(0xdb)?;
writer.write_u8(0xdc)?;
writer.write_u8(destination)?;
writer.write_bool(last)?;
writer.write_u16(length)?;
writer.write_all(&data[..length as usize])?;
}
Packet::CoreMgmtDropLinkAck { destination } => {
writer.write_u8(0xdc)?;
writer.write_u8(0xdd)?;
writer.write_u8(destination)?;
}
Packet::CoreMgmtDropLink => writer.write_u8(0xdd)?,
Packet::CoreMgmtDropLink => writer.write_u8(0xde)?,
Packet::CoreMgmtGetLogReply { last, length, data } => {
writer.write_u8(0xde)?;
writer.write_u8(0xdf)?;
writer.write_bool(last)?;
writer.write_u16(length)?;
writer.write_all(&data[0..length as usize])?;
}
Packet::CoreMgmtConfigReadReply { last, length, value } => {
writer.write_u8(0xdf)?;
writer.write_u8(0xe0)?;
writer.write_bool(last)?;
writer.write_u16(length)?;
writer.write_all(&value[0..length as usize])?;
}
Packet::CoreMgmtReply { succeeded } => {
writer.write_u8(0xe0)?;
writer.write_u8(0xe1)?;
writer.write_bool(succeeded)?;
}
}
@ -1252,7 +1268,8 @@ impl Packet {
| Packet::SubkernelMessageAck { .. }
| Packet::DmaPlaybackStatus { .. }
| Packet::SubkernelFinished { .. }
| Packet::CoreMgmtDropLinkAck { .. } => false,
| Packet::CoreMgmtDropLinkAck { .. }
| Packet::InjectionRequest { .. } => false,
_ => true,
}
}

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@ -85,10 +85,7 @@ unsafe fn get_ttype_entry(
encoding | DW_EH_PE_pcrel,
ttype_base,
)
.map(|v| match v {
ttype_base => None,
ttype_entry => Some(ttype_entry as *const u8),
})
.map(|v| (v != ttype_base).then(|| v as *const u8))
}
pub unsafe fn find_eh_action(

View File

@ -788,7 +788,11 @@ pub fn main(timer: GlobalTimer, cfg: Config) {
mgmt::start(
cfg.clone(),
restart_idle.clone(),
Some(mgmt::DrtioTuple(aux_mutex.clone(), drtio_routing_table.clone(), timer)),
Some(mgmt::DrtioContext(
aux_mutex.clone(),
drtio_routing_table.clone(),
timer,
)),
);
task::spawn(async move {

View File

@ -563,7 +563,6 @@ mod remote_coremgmt {
linkno: u8,
destination: u8,
) -> Result<()> {
info!("initited reboot request to satellite destination {}", destination);
let reply = drtio::aux_transact(
aux_mutex,
linkno,
@ -640,6 +639,32 @@ mod remote_coremgmt {
) -> Result<()> {
let mut image = &image[..];
let alloc_reply = drtio::aux_transact(
aux_mutex,
linkno,
routing_table,
&Packet::CoreMgmtFlashRequest {
destination: destination,
payload_length: image.len() as u32,
},
timer,
)
.await;
match alloc_reply {
Ok(Packet::CoreMgmtReply { succeeded: true }) => Ok(()),
Ok(packet) => {
error!("received unexpected aux packet: {:?}", packet);
write_i8(stream, Reply::Error as i8).await?;
Err(drtio::Error::UnexpectedReply)
}
Err(e) => {
error!("aux packet error ({})", e);
write_i8(stream, Reply::Error as i8).await?;
Err(drtio::Error::AuxError)
}
}?;
while !image.is_empty() {
let mut data = [0; MASTER_PAYLOAD_MAX_SIZE];
let len = image.read(&mut data).unwrap();
@ -649,7 +674,7 @@ mod remote_coremgmt {
aux_mutex,
linkno,
routing_table,
&Packet::CoreMgmtFlashRequest {
&Packet::CoreMgmtFlashAddDataRequest {
destination: destination,
last: last,
length: len as u16,
@ -856,10 +881,10 @@ mod local_coremgmt {
#[cfg(has_drtio)]
macro_rules! process {
($stream: ident, $drtio_tuple:ident, $destination:expr, $func:ident $(, $param:expr)*) => {{
($stream: ident, $drtio_context:ident, $destination:expr, $func:ident $(, $param:expr)*) => {{
if $destination == 0 {
local_coremgmt::$func($stream, $($param, )*).await
} else if let Some(DrtioTuple(ref aux_mutex, ref routing_table, timer)) = $drtio_tuple {
} else if let Some(DrtioContext(ref aux_mutex, ref routing_table, timer)) = $drtio_context {
let routing_table = routing_table.borrow();
let linkno = routing_table.0[$destination as usize][0] - 1 as u8;
remote_coremgmt::$func($stream, &aux_mutex, &routing_table, timer, linkno, $destination, $($param, )*).await
@ -873,20 +898,20 @@ macro_rules! process {
#[cfg(not(has_drtio))]
macro_rules! process {
($stream: ident, $drtio_tuple:ident, $destination:expr, $func:ident $(, $param:expr)*) => {{
($stream: ident, $drtio_context:ident, $destination:expr, $func:ident $(, $param:expr)*) => {{
local_coremgmt::$func($stream, $($param, )*).await
}}
}
#[derive(Clone)]
pub struct DrtioTuple(pub Rc<Mutex<bool>>, pub Rc<RefCell<RoutingTable>>, pub GlobalTimer);
pub struct DrtioContext(pub Rc<Mutex<bool>>, pub Rc<RefCell<RoutingTable>>, pub GlobalTimer);
async fn handle_connection(
stream: &mut TcpStream,
pull_id: Rc<RefCell<u32>>,
cfg: Rc<Config>,
restart_idle: Rc<Semaphore>,
_drtio_tuple: Option<DrtioTuple>,
_drtio_context: Option<DrtioContext>,
) -> Result<()> {
if !expect(&stream, b"ARTIQ management\n").await? {
return Err(Error::UnexpectedPattern);
@ -902,20 +927,20 @@ async fn handle_connection(
}
let msg: Request = FromPrimitive::from_i8(msg?).ok_or(Error::UnrecognizedPacket)?;
match msg {
Request::GetLog => process!(stream, _drtio_tuple, _destination, get_log),
Request::ClearLog => process!(stream, _drtio_tuple, _destination, clear_log),
Request::PullLog => process!(stream, _drtio_tuple, _destination, pull_log, &pull_id),
Request::GetLog => process!(stream, _drtio_context, _destination, get_log),
Request::ClearLog => process!(stream, _drtio_context, _destination, clear_log),
Request::PullLog => process!(stream, _drtio_context, _destination, pull_log, &pull_id),
Request::SetLogFilter => {
let lvl = read_log_level_filter(stream).await?;
process!(stream, _drtio_tuple, _destination, set_log_filter, lvl)
process!(stream, _drtio_context, _destination, set_log_filter, lvl)
}
Request::SetUartLogFilter => {
let lvl = read_log_level_filter(stream).await?;
process!(stream, _drtio_tuple, _destination, set_uart_log_filter, lvl)
process!(stream, _drtio_context, _destination, set_uart_log_filter, lvl)
}
Request::ConfigRead => {
let key = read_key(stream).await?;
process!(stream, _drtio_tuple, _destination, config_read, &cfg, &key)
process!(stream, _drtio_context, _destination, config_read, &cfg, &key)
}
Request::ConfigWrite => {
let key = read_key(stream).await?;
@ -928,7 +953,7 @@ async fn handle_connection(
read_chunk(stream, &mut buffer).await?;
process!(
stream,
_drtio_tuple,
_drtio_context,
_destination,
config_write,
&cfg,
@ -941,7 +966,7 @@ async fn handle_connection(
let key = read_key(stream).await?;
process!(
stream,
_drtio_tuple,
_drtio_context,
_destination,
config_remove,
&cfg,
@ -950,13 +975,13 @@ async fn handle_connection(
)
}
Request::Reboot => {
process!(stream, _drtio_tuple, _destination, reboot)
process!(stream, _drtio_context, _destination, reboot)
}
Request::ConfigErase => {
process!(stream, _drtio_tuple, _destination, config_erase)
process!(stream, _drtio_context, _destination, config_erase)
}
Request::DebugAllocator => {
process!(stream, _drtio_tuple, _destination, debug_allocator)
process!(stream, _drtio_context, _destination, debug_allocator)
}
Request::Flash => {
let len = read_i32(stream).await?;
@ -969,13 +994,13 @@ async fn handle_connection(
buffer.set_len(len as usize);
}
read_chunk(stream, &mut buffer).await?;
process!(stream, _drtio_tuple, _destination, image_write, &cfg, buffer)
process!(stream, _drtio_context, _destination, image_write, &cfg, buffer)
}
}?;
}
}
pub fn start(cfg: Rc<Config>, restart_idle: Rc<Semaphore>, drtio_tuple: Option<DrtioTuple>) {
pub fn start(cfg: Rc<Config>, restart_idle: Rc<Semaphore>, drtio_context: Option<DrtioContext>) {
task::spawn(async move {
let pull_id = Rc::new(RefCell::new(0u32));
loop {
@ -983,10 +1008,10 @@ pub fn start(cfg: Rc<Config>, restart_idle: Rc<Semaphore>, drtio_tuple: Option<D
let pull_id = pull_id.clone();
let cfg = cfg.clone();
let restart_idle = restart_idle.clone();
let drtio_tuple = drtio_tuple.clone();
let drtio_context = drtio_context.clone();
task::spawn(async move {
info!("received connection");
let _ = handle_connection(&mut stream, pull_id, cfg, restart_idle, drtio_tuple)
let _ = handle_connection(&mut stream, pull_id, cfg, restart_idle, drtio_context)
.await
.map_err(|e| warn!("connection terminated: {:?}", e));
let _ = stream.flush().await;

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@ -1281,6 +1281,24 @@ fn process_aux_packet(
drtioaux::send(0, &drtioaux::Packet::CoreMgmtReply { succeeded: false })
}
drtioaux::Packet::CoreMgmtFlashRequest {
destination: _destination,
payload_length,
} => {
forward!(
router,
_routing_table,
_destination,
*rank,
*self_destination,
_repeaters,
&packet,
timer
);
core_manager.allocate_image_buffer(payload_length as usize);
drtioaux::send(0, &drtioaux::Packet::CoreMgmtReply { succeeded: true })
}
drtioaux::Packet::CoreMgmtFlashAddDataRequest {
destination: _destination,
last,
length,

View File

@ -115,6 +115,10 @@ impl<'a> Manager<'_> {
.map_err(|err| warn!("failed to erase: {:?}", err))
}
pub fn allocate_image_buffer(&mut self, image_size: usize) {
self.image_payload = Vec::with_capacity(image_size);
}
pub fn add_image_data(&mut self, data: &[u8], data_len: usize) {
self.image_payload.extend(&data[..data_len]);
}