forked from M-Labs/artiq-zynq
move registers too
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parent
805beeacaf
commit
5f1c7a41f2
@ -318,6 +318,7 @@ class GenericMaster(SoCCore):
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4 * 2**(self.csr_address_width),
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4 * 2**(self.csr_address_width),
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self.drtio_axi2csr.bus)
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self.drtio_axi2csr.bus)
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self.drtio_csr_devices = []
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self.drtio_csr_group = []
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self.drtio_csr_group = []
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self.drtioaux_csr_group = []
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self.drtioaux_csr_group = []
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self.drtioaux_memory_group = []
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self.drtioaux_memory_group = []
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@ -335,11 +336,11 @@ class GenericMaster(SoCCore):
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core = cdr(DRTIOMaster(self.rtio_tsc, self.gt_drtio.channels[i]))
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core = cdr(DRTIOMaster(self.rtio_tsc, self.gt_drtio.channels[i]))
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setattr(self.submodules, core_name, core)
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setattr(self.submodules, core_name, core)
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self.drtio_cri.append(core.cri)
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self.drtio_cri.append(core.cri)
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self.csr_devices.append(core_name)
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self.drtio_csr_devices.append(core_name)
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coreaux = cdr(drtio_aux_controller.DRTIOAuxControllerBare(core.link_layer))
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coreaux = cdr(drtio_aux_controller.DRTIOAuxControllerBare(core.link_layer))
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setattr(self.submodules, coreaux_name, coreaux)
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setattr(self.submodules, coreaux_name, coreaux)
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self.csr_devices.append(coreaux_name)
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self.drtio_csr_devices.append(coreaux_name)
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size = coreaux.get_mem_size()
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size = coreaux.get_mem_size()
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memory_address = self.drtio_axi2csr.register_port(coreaux.get_tx_port(), size)
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memory_address = self.drtio_axi2csr.register_port(coreaux.get_tx_port(), size)
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@ -436,6 +437,29 @@ class GenericMaster(SoCCore):
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self.add_csr_group("drtioaux", self.drtioaux_csr_group)
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self.add_csr_group("drtioaux", self.drtioaux_csr_group)
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self.add_memory_group("drtioaux_mem", self.drtioaux_memory_group)
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self.add_memory_group("drtioaux_mem", self.drtioaux_memory_group)
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def get_drtio_csr_dev_address(self, name, memory):
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if memory is not None:
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name = "_".join([name, memory.name_override])
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try:
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return self.drtio_csr_devices.index(name)
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except ValueError:
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return None
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def do_finalize(self):
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SoCCore.do_finalize(self)
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self.submodules.drtio_csrbankarray = csr_bus.CSRBankArray(
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self, self.get_drtio_csr_dev_address,
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data_width=self.csr_data_width,
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address_width=self.csr_address_width)
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self.submodules.csrcon = csr_bus.Interconnect(
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self.drtio_axi2csr.csr, self.drtio_csrbankarray.get_buses())
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for name, csrs, mapaddr, rmap in self.drtio_csrbankarray.banks:
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self.add_csr_region(
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name, (self.mem_map["axi"] + 0x800 * mapaddr),
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self.csr_data_width, csrs)
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class GenericSatellite(SoCCore):
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class GenericSatellite(SoCCore):
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def __init__(self, description, acpki=False):
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def __init__(self, description, acpki=False):
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