From 5f1c7a41f2281900ed47b63284dd7afa54db6af5 Mon Sep 17 00:00:00 2001
From: mwojcik <mw@m-labs.hk>
Date: Fri, 29 Nov 2024 16:43:39 +0800
Subject: [PATCH] move registers too

---
 src/gateware/kasli_soc.py | 28 ++++++++++++++++++++++++++--
 1 file changed, 26 insertions(+), 2 deletions(-)

diff --git a/src/gateware/kasli_soc.py b/src/gateware/kasli_soc.py
index 26d4300..0b1b372 100755
--- a/src/gateware/kasli_soc.py
+++ b/src/gateware/kasli_soc.py
@@ -318,6 +318,7 @@ class GenericMaster(SoCCore):
                           4 * 2**(self.csr_address_width),
                           self.drtio_axi2csr.bus)
 
+        self.drtio_csr_devices = []
         self.drtio_csr_group = []
         self.drtioaux_csr_group = []
         self.drtioaux_memory_group = []
@@ -335,11 +336,11 @@ class GenericMaster(SoCCore):
             core = cdr(DRTIOMaster(self.rtio_tsc, self.gt_drtio.channels[i]))
             setattr(self.submodules, core_name, core)
             self.drtio_cri.append(core.cri)
-            self.csr_devices.append(core_name)
+            self.drtio_csr_devices.append(core_name)
 
             coreaux = cdr(drtio_aux_controller.DRTIOAuxControllerBare(core.link_layer))
             setattr(self.submodules, coreaux_name, coreaux)
-            self.csr_devices.append(coreaux_name)
+            self.drtio_csr_devices.append(coreaux_name)
 
             size = coreaux.get_mem_size()
             memory_address = self.drtio_axi2csr.register_port(coreaux.get_tx_port(), size)
@@ -436,6 +437,29 @@ class GenericMaster(SoCCore):
         self.add_csr_group("drtioaux", self.drtioaux_csr_group)
         self.add_memory_group("drtioaux_mem", self.drtioaux_memory_group)
 
+    def get_drtio_csr_dev_address(self, name, memory):
+        if memory is not None:
+            name = "_".join([name, memory.name_override])
+        try:
+            return self.drtio_csr_devices.index(name)
+        except ValueError:
+            return None
+
+    def do_finalize(self):
+        SoCCore.do_finalize(self)
+        self.submodules.drtio_csrbankarray = csr_bus.CSRBankArray(
+            self, self.get_drtio_csr_dev_address,
+            data_width=self.csr_data_width,
+            address_width=self.csr_address_width)
+
+        self.submodules.csrcon = csr_bus.Interconnect(
+            self.drtio_axi2csr.csr, self.drtio_csrbankarray.get_buses())
+
+        for name, csrs, mapaddr, rmap in self.drtio_csrbankarray.banks:
+            self.add_csr_region(
+                name, (self.mem_map["axi"] + 0x800 * mapaddr),
+                self.csr_data_width, csrs)
+
 
 class GenericSatellite(SoCCore):
     def __init__(self, description, acpki=False):