morgan/zynq-rs
1
0
Fork 0
forked from M-Labs/zynq-rs
Code Pull Requests Activity
Bare-metal Rust on Zynq-7000
576 Commits 5 Branches 0 Tags 1.5 MiB
Rust 90.6%
Nix 6.8%
Assembly 2.5%
759bf95a76
Go to file
Sebastien Bourdeauducq 759bf95a76 add Kasli-SoC POR control program
2021-05-29 17:43:21 +08:00
.cargo cargo: remove unmaintained runner 2020-09-09 15:01:39 +08:00
experiments libsupport_zynq: fix stack pointer problems 2021-01-28 12:33:06 +08:00
libasync libasync: provide get/set ack_delay (new in smoltcp 0.7.0) 2021-02-08 03:06:51 +01:00
libboard_zynq libboard_zynq: work around Kasli-SoC MDIO breakage (#78) 2021-05-29 12:50:28 +08:00
libconfig add feature target_kasli_soc to libsupport_zynq, libconfig, experiments, szl, default.nix 2020-11-19 19:41:38 +01:00
libcortex_a9 libcortex_a9: added interrupt_handler macro 2021-01-28 11:41:34 +08:00
libregister libregister: allow rustdoc for register! macro 2020-11-19 20:26:18 +01:00
libsupport_zynq libsupport_zynq: fix stack pointer problems 2021-01-28 12:33:06 +08:00
nix update Rust 2021-02-03 22:42:00 +01:00
openocd openocd: fix Kasli-SoC nSRST 2021-05-29 12:17:59 +08:00
szl szl: update copyright year 2021-05-29 14:01:29 +08:00
.gitignore remove zc706.elf from gitignore 2020-01-16 02:13:11 +08:00
armv7-none-eabihf.json define custom target, use with cargo-xbuild 2019-08-06 22:03:04 +02:00
Cargo.lock use updated upstream core_io 2021-05-29 14:09:11 +08:00
Cargo.toml use updated upstream core_io 2021-05-29 14:09:11 +08:00
default.nix update cargosha256 2021-05-29 14:13:51 +08:00
kasli_soc_por.py add Kasli-SoC POR control program 2021-05-29 17:43:21 +08:00
LICENSE LGPLv3 2021-04-06 16:46:38 +08:00
README.md LGPLv3 2021-04-06 16:46:38 +08:00
remote_run.sh remote_run.sh: clean up getopts 2020-11-18 17:45:43 +08:00
shell.nix libsupport_zynq: custom memcpy 2021-01-15 17:08:14 +08:00
xbuild_writable_lockfile.diff patch cargo-xbuild to ensure copied Cargo.lock is writable 2020-10-13 18:27:52 +08:00

README.md

Bare-metal Rust on Zynq-7000

Supported features:

  • Clocking setup
  • UART
  • SDRAM setup
  • Ethernet with smoltcp and async-await on TCP sockets
  • SD card
  • PL programming and startup
  • Pure Rust SZL first-stage bootloader, with SD boot and netboot
  • Control of second CPU core and message passing, with async-await support

Supported boards:

  • ZC706
  • Red Pitaya
  • Cora Z7-10 (seems to also run on Cora Z7-07S, including dual-core support)

Build

nix-shell --command "cargo xbuild --release -p experiments"

Currently the ELF output is placed at target/armv7-none-eabihf/release/experiments

Debug

Running on the ZC706

nix-shell --command "cargo xbuild --release -p experiments"
cd openocd
openocd -f zc706.cfg

Running on the Cora Z7-10

nix-shell --command "cd experiments && cargo xbuild --release --no-default-features --features=target_coraz7"
cd openocd
openocd -f cora-z7-10.cfg

Loading a bitstream into volatile memory

openocd -f zc706.cfg -c "pld load 0 blinker_migen.bit; exit"

License

Copyright (C) 2019-2021 M-Labs Limited. Released under the GNU LGPL v3. See the LICENSE file for details.