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Bare-metal Rust on Zynq-7000
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Sebastien Bourdeauducq 759bf95a76 add Kasli-SoC POR control program 2021-05-29 17:43:21 +08:00
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experiments libsupport_zynq: fix stack pointer problems 2021-01-28 12:33:06 +08:00
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openocd openocd: fix Kasli-SoC nSRST 2021-05-29 12:17:59 +08:00
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armv7-none-eabihf.json define custom target, use with cargo-xbuild 2019-08-06 22:03:04 +02:00
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kasli_soc_por.py add Kasli-SoC POR control program 2021-05-29 17:43:21 +08:00
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README.md

Bare-metal Rust on Zynq-7000

Supported features:

  • Clocking setup
  • UART
  • SDRAM setup
  • Ethernet with smoltcp and async-await on TCP sockets
  • SD card
  • PL programming and startup
  • Pure Rust SZL first-stage bootloader, with SD boot and netboot
  • Control of second CPU core and message passing, with async-await support

Supported boards:

  • ZC706
  • Red Pitaya
  • Cora Z7-10 (seems to also run on Cora Z7-07S, including dual-core support)

Build

nix-shell --command "cargo xbuild --release -p experiments"

Currently the ELF output is placed at target/armv7-none-eabihf/release/experiments

Debug

Running on the ZC706

nix-shell --command "cargo xbuild --release -p experiments"
cd openocd
openocd -f zc706.cfg

Running on the Cora Z7-10

nix-shell --command "cd experiments && cargo xbuild --release --no-default-features --features=target_coraz7"
cd openocd
openocd -f cora-z7-10.cfg

Loading a bitstream into volatile memory

openocd -f zc706.cfg -c "pld load 0 blinker_migen.bit; exit"

License

Copyright (C) 2019-2021 M-Labs Limited. Released under the GNU LGPL v3. See the LICENSE file for details.