forked from M-Labs/zynq-rs
621 lines
18 KiB
Rust
621 lines
18 KiB
Rust
use core::ops::{Deref, DerefMut};
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use log::{error, info, warn};
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use libregister::*;
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use super::slcr;
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use super::clocks::Clocks;
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pub mod phy;
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use phy::{Phy, PhyAccess};
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mod regs;
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pub mod rx;
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pub mod tx;
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/// Size of all the buffers
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pub const MTU: usize = 1536;
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/// Maximum MDC clock
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const MAX_MDC: u32 = 2_500_000;
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const TX_10: u32 = 10_000_000;
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const TX_100: u32 = 25_000_000;
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/// Clock for GbE
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const TX_1000: u32 = 125_000_000;
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#[derive(Clone)]
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#[repr(C, align(0x20))]
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pub struct Buffer(pub [u8; MTU]);
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impl Buffer {
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pub fn new() -> Self {
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Buffer([0; MTU])
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}
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}
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impl Deref for Buffer {
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type Target = [u8];
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fn deref(&self) -> &Self::Target {
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&self.0
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}
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}
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impl DerefMut for Buffer {
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fn deref_mut(&mut self) -> &mut <Self as Deref>::Target {
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&mut self.0
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}
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}
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pub struct Eth<'r, RX, TX> {
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rx: RX,
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tx: TX,
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inner: EthInner<'r>,
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phy: Phy,
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}
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impl<'r> Eth<'r, (), ()> {
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pub fn default(macaddr: [u8; 6]) -> Self {
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slcr::RegisterBlock::unlocked(|slcr| {
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// Manual example: 0x0000_1280
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// MDIO
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slcr.mio_pin_53.write(
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slcr::MioPin53::zeroed()
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.l3_sel(0b100)
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.io_type(slcr::IoBufferType::Lvcmos18)
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.pullup(true)
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);
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// MDC
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slcr.mio_pin_52.write(
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slcr::MioPin52::zeroed()
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.l3_sel(0b100)
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.io_type(slcr::IoBufferType::Lvcmos18)
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.pullup(true)
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);
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// Manual example: 0x0000_3902
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// TX_CLK
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slcr.mio_pin_16.write(
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slcr::MioPin16::zeroed()
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.l0_sel(true)
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.speed(true)
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.io_type(slcr::IoBufferType::Hstl)
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.pullup(true)
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.disable_rcvr(true)
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);
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// TX_CTRL
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slcr.mio_pin_21.write(
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slcr::MioPin21::zeroed()
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.l0_sel(true)
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.speed(true)
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.io_type(slcr::IoBufferType::Hstl)
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.pullup(true)
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.disable_rcvr(true)
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);
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// TXD3
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slcr.mio_pin_20.write(
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slcr::MioPin20::zeroed()
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.l0_sel(true)
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.speed(true)
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.io_type(slcr::IoBufferType::Hstl)
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.pullup(true)
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.disable_rcvr(true)
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);
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// TXD2
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slcr.mio_pin_19.write(
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slcr::MioPin19::zeroed()
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.l0_sel(true)
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.speed(true)
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.io_type(slcr::IoBufferType::Hstl)
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.pullup(true)
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.disable_rcvr(true)
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);
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// TXD1
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slcr.mio_pin_18.write(
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slcr::MioPin18::zeroed()
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.l0_sel(true)
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.speed(true)
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.io_type(slcr::IoBufferType::Hstl)
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.pullup(true)
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.disable_rcvr(true)
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);
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// TXD0
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slcr.mio_pin_17.write(
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slcr::MioPin17::zeroed()
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.l0_sel(true)
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.speed(true)
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.io_type(slcr::IoBufferType::Hstl)
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.pullup(true)
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.disable_rcvr(true)
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);
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// Manual example: 0x0000_1903
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// RX_CLK
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slcr.mio_pin_22.write(
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slcr::MioPin22::zeroed()
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.tri_enable(true)
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.l0_sel(true)
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.io_type(slcr::IoBufferType::Hstl)
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.pullup(true)
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);
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// RX_CTRL
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slcr.mio_pin_27.write(
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slcr::MioPin27::zeroed()
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.tri_enable(true)
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.l0_sel(true)
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.io_type(slcr::IoBufferType::Hstl)
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.pullup(true)
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);
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// RXD3
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slcr.mio_pin_26.write(
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slcr::MioPin26::zeroed()
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.tri_enable(true)
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.l0_sel(true)
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.io_type(slcr::IoBufferType::Hstl)
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.pullup(true)
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);
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// RXD2
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slcr.mio_pin_25.write(
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slcr::MioPin25::zeroed()
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.tri_enable(true)
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.l0_sel(true)
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.io_type(slcr::IoBufferType::Hstl)
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.pullup(true)
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);
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// RXD1
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slcr.mio_pin_24.write(
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slcr::MioPin24::zeroed()
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.tri_enable(true)
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.l0_sel(true)
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.io_type(slcr::IoBufferType::Hstl)
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.pullup(true)
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);
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// RXD0
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slcr.mio_pin_23.write(
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slcr::MioPin23::zeroed()
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.tri_enable(true)
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.l0_sel(true)
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.io_type(slcr::IoBufferType::Hstl)
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.pullup(true)
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);
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// VREF internal generator
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slcr.gpiob_ctrl.write(
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slcr::GpiobCtrl::zeroed()
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.vref_en(true)
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);
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});
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Self::gem0(macaddr)
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}
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pub fn gem0(macaddr: [u8; 6]) -> Self {
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Self::setup_gem0_clock(TX_1000);
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let regs = regs::RegisterBlock::gem0();
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Self::from_regs(regs, macaddr)
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}
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pub fn gem1(macaddr: [u8; 6]) -> Self {
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Self::setup_gem1_clock(TX_1000);
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let regs = regs::RegisterBlock::gem1();
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Self::from_regs(regs, macaddr)
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}
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fn from_regs(regs: &'r mut regs::RegisterBlock, macaddr: [u8; 6]) -> Self {
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let mut inner = EthInner {
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regs,
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link: None,
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};
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inner.init();
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inner.configure(macaddr);
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let phy = Phy::find(&mut inner).expect("phy");
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phy.reset(&mut inner);
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phy.restart_autoneg(&mut inner);
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Eth {
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rx: (),
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tx: (),
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inner,
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phy,
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}
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}
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}
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impl<'r, RX, TX> Eth<'r, RX, TX> {
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pub fn setup_gem0_clock(tx_clock: u32) {
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let io_pll = Clocks::get().io;
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let d0 = ((tx_clock - 1 + io_pll) / tx_clock).max(1).min(63);
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let d1 = (io_pll / tx_clock / d0).max(1).min(63);
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slcr::RegisterBlock::unlocked(|slcr| {
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slcr.gem0_clk_ctrl.write(
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// 0x0050_0801: 8, 5: 100 Mb/s
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// ...: 8, 1: 1000 Mb/s
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slcr::GemClkCtrl::zeroed()
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.clkact(true)
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.srcsel(slcr::PllSource::IoPll)
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.divisor(d0 as u8)
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.divisor1(d1 as u8)
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);
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// Enable gem0 recv clock
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slcr.gem0_rclk_ctrl.write(
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// 0x0000_0801
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slcr::RclkCtrl::zeroed()
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.clkact(true)
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);
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});
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}
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pub fn setup_gem1_clock(tx_clock: u32) {
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let io_pll = Clocks::get().io;
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let d0 = ((tx_clock - 1 + io_pll) / tx_clock).max(1).min(63);
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let d1 = (io_pll / tx_clock / d0).max(1).min(63);
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slcr::RegisterBlock::unlocked(|slcr| {
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slcr.gem1_clk_ctrl.write(
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slcr::GemClkCtrl::zeroed()
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.clkact(true)
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.srcsel(slcr::PllSource::IoPll)
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.divisor(d0 as u8)
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.divisor1(d1 as u8)
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);
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// Enable gem1 recv clock
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slcr.gem1_rclk_ctrl.write(
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// 0x0000_0801
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slcr::RclkCtrl::zeroed()
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.clkact(true)
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);
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});
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}
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pub fn start_rx(self, rx_size: usize) -> Eth<'r, rx::DescList, TX> {
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let new_self = Eth {
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rx: rx::DescList::new(rx_size),
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tx: self.tx,
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inner: self.inner,
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phy: self.phy,
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};
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let list_addr = new_self.rx.list_addr();
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assert!(list_addr & 0b11 == 0);
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new_self.inner.regs.rx_qbar.write(
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regs::RxQbar::zeroed()
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.rx_q_baseaddr(list_addr >> 2)
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);
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new_self.inner.regs.net_ctrl.modify(|_, w|
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w.rx_en(true)
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);
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new_self
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}
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pub fn start_tx(self, tx_size: usize) -> Eth<'r, RX, tx::DescList> {
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let new_self = Eth {
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rx: self.rx,
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tx: tx::DescList::new(tx_size),
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inner: self.inner,
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phy: self.phy,
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};
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let list_addr = &new_self.tx.list_addr();
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assert!(list_addr & 0b11 == 0);
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new_self.inner.regs.tx_qbar.write(
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regs::TxQbar::zeroed()
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.tx_q_baseaddr(list_addr >> 2)
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);
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new_self.inner.regs.net_ctrl.modify(|_, w|
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w.tx_en(true)
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);
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new_self
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}
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}
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impl<'r, TX> Eth<'r, rx::DescList, TX> {
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pub fn recv_next<'s: 'p, 'p>(&'s mut self) -> Result<Option<rx::PktRef<'p>>, rx::Error> {
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let status = self.inner.regs.rx_status.read();
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if status.hresp_not_ok() {
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// Clear
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self.inner.regs.rx_status.write(
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regs::RxStatus::zeroed()
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.hresp_not_ok(true)
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);
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return Err(rx::Error::HrespNotOk);
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}
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if status.rx_overrun() {
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// Clear
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self.inner.regs.rx_status.write(
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regs::RxStatus::zeroed()
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.rx_overrun(true)
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);
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return Err(rx::Error::RxOverrun);
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}
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if status.buffer_not_avail() {
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// Clear
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self.inner.regs.rx_status.write(
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regs::RxStatus::zeroed()
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.buffer_not_avail(true)
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);
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return Err(rx::Error::BufferNotAvail);
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}
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if status.frame_recd() {
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let result = self.rx.recv_next();
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match result {
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Ok(None) => {
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// No packet, clear status bit
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self.inner.regs.rx_status.write(
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regs::RxStatus::zeroed()
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.frame_recd(true)
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);
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}
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_ => {}
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}
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result
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} else {
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self.inner.check_link_change(&self.phy);
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Ok(None)
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}
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}
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}
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impl<'r, RX> Eth<'r, RX, tx::DescList> {
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pub fn send<'s: 'p, 'p>(&'s mut self, length: usize) -> Option<tx::PktRef<'p>> {
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self.tx.send(self.inner.regs, length)
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}
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}
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impl<'r, 'a> smoltcp::phy::Device<'a> for &mut Eth<'r, rx::DescList, tx::DescList> {
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type RxToken = rx::PktRef<'a>;
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type TxToken = tx::Token<'a>;
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fn capabilities(&self) -> smoltcp::phy::DeviceCapabilities {
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use smoltcp::phy::{DeviceCapabilities, ChecksumCapabilities, Checksum};
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let mut checksum_caps = ChecksumCapabilities::default();
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checksum_caps.ipv4 = Checksum::Both;
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checksum_caps.tcp = Checksum::Both;
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checksum_caps.udp = Checksum::Both;
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let mut caps = DeviceCapabilities::default();
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caps.max_transmission_unit = MTU;
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caps.max_burst_size = Some(self.rx.len().min(self.tx.len()));
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caps.checksum = checksum_caps;
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caps
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}
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fn receive(&'a mut self) -> Option<(Self::RxToken, Self::TxToken)> {
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match self.rx.recv_next() {
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Ok(Some(pktref)) => {
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let tx_token = tx::Token {
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regs: self.inner.regs,
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desc_list: &mut self.tx,
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};
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Some((pktref, tx_token))
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}
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Ok(None) => {
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self.inner.check_link_change(&self.phy);
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None
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}
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Err(e) => {
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error!("eth recv error: {:?}", e);
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None
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}
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}
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}
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fn transmit(&'a mut self) -> Option<Self::TxToken> {
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Some(tx::Token {
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regs: self.inner.regs,
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desc_list: &mut self.tx,
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})
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}
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}
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struct EthInner<'r> {
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regs: &'r mut regs::RegisterBlock,
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link: Option<phy::Link>,
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}
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impl<'r> EthInner<'r> {
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fn init(&mut self) {
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// Clear the Network Control register.
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self.regs.net_ctrl.write(regs::NetCtrl::zeroed());
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self.regs.net_ctrl.write(regs::NetCtrl::zeroed().clear_stat_regs(true));
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// Clear the Status registers.
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self.regs.rx_status.write(
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regs::RxStatus::zeroed()
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.buffer_not_avail(true)
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.frame_recd(true)
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.rx_overrun(true)
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.hresp_not_ok(true)
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);
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self.regs.tx_status.write(
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regs::TxStatus::zeroed()
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.used_bit_read(true)
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.collision(true)
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.retry_limit_exceeded(true)
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.tx_go(true)
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.tx_corr_ahb_err(true)
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.tx_complete(true)
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.tx_under_run(true)
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.late_collision(true)
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// not in the manual:
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.hresp_not_ok(true)
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);
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// Disable all interrupts.
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self.regs.intr_dis.write(
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regs::IntrDis::zeroed()
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.mgmt_done(true)
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.rx_complete(true)
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.rx_used_read(true)
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.tx_used_read(true)
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.tx_underrun(true)
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.retry_ex_late_collisn(true)
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.tx_corrupt_ahb_err(true)
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.tx_complete(true)
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.link_chng(true)
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.rx_overrun(true)
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.hresp_not_ok(true)
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.pause_nonzeroq(true)
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.pause_zero(true)
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.pause_tx(true)
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.ex_intr(true)
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.autoneg_complete(true)
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.partner_pg_rx(true)
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.delay_req_rx(true)
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.sync_rx(true)
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.delay_req_tx(true)
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.sync_tx(true)
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.pdelay_req_rx(true)
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.pdelay_resp_rx(true)
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.pdelay_req_tx(true)
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.pdelay_resp_tx(true)
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.tsu_sec_incr(true)
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);
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// Clear the buffer queues.
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self.regs.rx_qbar.write(
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regs::RxQbar::zeroed()
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);
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self.regs.tx_qbar.write(
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regs::TxQbar::zeroed()
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);
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|
}
|
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|
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fn configure(&mut self, macaddr: [u8; 6]) {
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let clocks = Clocks::get();
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let mdc_clk_div = (clocks.cpu_1x() / MAX_MDC) + 1;
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self.regs.net_cfg.write(
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regs::NetCfg::zeroed()
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.full_duplex(true)
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.gige_en(true)
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.speed(true)
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.no_broadcast(false)
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.multi_hash_en(true)
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// Promiscuous mode (TODO?)
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.copy_all(true)
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// Remove 4-byte Frame CheckSum
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.fcs_remove(true)
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// RX checksum offload
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.rx_chksum_offld_en(true)
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// One of the slower speeds
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.mdc_clk_div((mdc_clk_div >> 4).min(0b111) as u8)
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);
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let macaddr_msbs =
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(u16::from(macaddr[0]) << 8) |
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u16::from(macaddr[1]);
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let macaddr_lsbs =
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(u32::from(macaddr[2]) << 24) |
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(u32::from(macaddr[3]) << 16) |
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(u32::from(macaddr[4]) << 8) |
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u32::from(macaddr[5]);
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self.regs.spec_addr1_top.write(
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regs::SpecAddrTop::zeroed()
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.addr_msbs(macaddr_msbs)
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);
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self.regs.spec_addr1_bot.write(
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regs::SpecAddrBot::zeroed()
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|
.addr_lsbs(macaddr_lsbs)
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);
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|
|
|
|
self.regs.dma_cfg.write(
|
|
regs::DmaCfg::zeroed()
|
|
// 1536 bytes
|
|
.ahb_mem_rx_buf_size((MTU >> 6) as u8)
|
|
// 8 KB
|
|
.rx_pktbuf_memsz_sel(0x3)
|
|
// 4 KB
|
|
.tx_pktbuf_memsz_sel(true)
|
|
// TX checksum offload
|
|
.csum_gen_offload_en(true)
|
|
// Little-endian
|
|
.ahb_endian_swp_mgmt_en(false)
|
|
// INCR16 AHB burst
|
|
.ahb_fixed_burst_len(0x10)
|
|
);
|
|
|
|
self.regs.net_ctrl.write(
|
|
regs::NetCtrl::zeroed()
|
|
.mgmt_port_en(true)
|
|
);
|
|
}
|
|
|
|
|
|
fn wait_phy_idle(&self) {
|
|
while !self.regs.net_status.read().phy_mgmt_idle() {}
|
|
}
|
|
|
|
|
|
fn check_link_change(&mut self, phy: &Phy) {
|
|
// As the PHY access takes some time, exit early if there was
|
|
// already a link. TODO: check once per second.
|
|
if self.link.is_some() {
|
|
return
|
|
}
|
|
|
|
let link = phy.get_link(self);
|
|
|
|
// Check link state transition
|
|
if self.link != link {
|
|
match &link {
|
|
Some(link) => {
|
|
info!("eth: got {:?}", link);
|
|
|
|
use phy::LinkSpeed::*;
|
|
let txclock = match link.speed {
|
|
S10 => TX_10,
|
|
S100 => TX_100,
|
|
S1000 => TX_1000,
|
|
};
|
|
Eth::<(), ()>::setup_gem0_clock(txclock);
|
|
/* .full_duplex(false) doesn't work even if
|
|
half duplex has been negotiated. */
|
|
self.regs.net_cfg.modify(|_, w| w
|
|
.full_duplex(true)
|
|
.gige_en(link.speed == S1000)
|
|
.speed(link.speed != S10)
|
|
);
|
|
}
|
|
None => {
|
|
warn!("eth: link lost");
|
|
phy.modify_control(self, |control|
|
|
control.set_autoneg_enable(true)
|
|
.set_restart_autoneg(true)
|
|
);
|
|
}
|
|
}
|
|
|
|
self.link = link;
|
|
}
|
|
}
|
|
}
|
|
|
|
impl<'r> PhyAccess for EthInner<'r> {
|
|
fn read_phy(&mut self, addr: u8, reg: u8) -> u16 {
|
|
self.wait_phy_idle();
|
|
self.regs.phy_maint.write(
|
|
regs::PhyMaint::zeroed()
|
|
.clause_22(true)
|
|
.operation(regs::PhyOperation::Read)
|
|
.phy_addr(addr)
|
|
.reg_addr(reg)
|
|
.must_10(0b10)
|
|
);
|
|
self.wait_phy_idle();
|
|
self.regs.phy_maint.read().data()
|
|
}
|
|
|
|
fn write_phy(&mut self, addr: u8, reg: u8, data: u16) {
|
|
self.wait_phy_idle();
|
|
self.regs.phy_maint.write(
|
|
regs::PhyMaint::zeroed()
|
|
.clause_22(true)
|
|
.operation(regs::PhyOperation::Write)
|
|
.phy_addr(addr)
|
|
.reg_addr(reg)
|
|
.must_10(0b10)
|
|
.data(data)
|
|
);
|
|
self.wait_phy_idle();
|
|
}
|
|
}
|
|
|
|
|