15 Commits

Author	SHA1	Message	Date
Astro	81a892b618	eth: recv_next()	2019-06-10 02:44:29 +02:00
Astro	f92ea3b99d	eth: start_tx	2019-06-09 20:28:33 +02:00
Astro	f07a541c99	eth: model rx/tx state with type parameters	2019-06-09 20:10:41 +02:00
Astro	74bd81f87f	eth: add safety asserts	2019-06-09 02:23:37 +02:00
Astro	824e91e6cb	eth: rx/tx desc list, start_rx	2019-06-09 01:02:10 +02:00
Astro	b9ca9324f0	eth: fix initialization	2019-06-04 23:48:33 +02:00
Astro	b13bf72c17	eth: begin phy communication	2019-05-30 02:42:42 +02:00
Astro	c0610ad66a	slcr: init gem* rclk/clk	2019-05-30 02:26:19 +02:00
Astro	d10ffe9eb9	eth: setup mio_pins, configure net_cfg	2019-05-25 03:06:39 +02:00
Astro	6bf210366a	regs: properly emit doc_comments	2019-05-24 23:49:49 +02:00
Astro	56c2f1d833	eth: add net_status, phy_maint registers	2019-05-24 00:20:59 +02:00
Astro	ad77e3dc04	eth: add net_cfg register	2019-05-24 00:06:29 +02:00
Astro	402b8c9ab1	eth: no unsafe, note, add qbar register fields	2019-05-23 23:18:36 +02:00
Astro	785e726661	RegisterW/RegisterRW: required &mut self for safety	2019-05-23 18:01:18 +02:00
Astro	b754581452	eth: add regs and init	2019-05-07 19:28:33 +02:00