forked from M-Labs/zynq-rs
zynq::flash: add rdsr1()
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@ -14,6 +14,8 @@ const SINGLE_CAPACITY: u32 = 16 * 1024 * 1024;
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/// Instruction: Read Configure Register
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/// Instruction: Read Configure Register
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const INST_RDCR: u8 = 0x35;
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const INST_RDCR: u8 = 0x35;
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/// Instruction: Read Status Register-1
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const INST_RDSR1: u8 = 0x05;
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/// Instruction: Read Identification
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/// Instruction: Read Identification
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const INST_RDID: u8 = 0x9F;
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const INST_RDID: u8 = 0x9F;
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@ -355,6 +357,14 @@ impl Flash<Manual> {
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.next().unwrap() as u8
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.next().unwrap() as u8
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}
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}
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/// Read Status Register-1
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pub fn rdsr1(&mut self) -> u8 {
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let args = Some(INST_RDSR1 as u8);
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self.transfer(args.into_iter(), 2)
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.bytes_transfer().skip(1)
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.next().unwrap()
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}
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/// Read Identifiaction
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/// Read Identifiaction
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pub fn rdid(&mut self) -> core::iter::Skip<BytesTransfer<Transfer<core::option::IntoIter<u32>, u32>>> {
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pub fn rdid(&mut self) -> core::iter::Skip<BytesTransfer<Transfer<core::option::IntoIter<u32>, u32>>> {
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let args = Some((INST_RDID as u32) << 24);
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let args = Some((INST_RDID as u32) << 24);
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