forked from M-Labs/zynq-rs
zynq::flash: add read_reg_until()
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0d1cf04a34
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@ -359,9 +359,40 @@ impl Flash<Manual> {
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pub fn read_reg<R: SpiFlashRegister>(&mut self) -> R {
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let args = Some(R::inst_code());
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let transfer = self.transfer(args.into_iter(), R::transfer_len())
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.bytes_transfer().skip(1);
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R::new(transfer)
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let transfer = self.transfer(args.into_iter(), 2)
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.bytes_transfer();
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R::new(transfer.skip(1).next().unwrap())
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}
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pub fn read_reg_until<R, F, A>(&mut self, f: F) -> A
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where
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R: SpiFlashRegister,
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F: Fn(R) -> Option<A>,
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{
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let mut result = None;
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while result.is_none() {
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let args = Some(R::inst_code());
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for b in self.transfer(args.into_iter(), 32)
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.bytes_transfer().skip(1) {
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result = f(R::new(b));
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if result.is_none() {
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break;
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}
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}
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}
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result.unwrap()
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}
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/// Status Register-1 remains `0x00` immediately after invoking a command.
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fn wait_while_sr1_zeroed(&mut self) -> SR1 {
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self.read_reg_until::<SR1, _, SR1>(|sr1|
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if sr1.is_zeroed() {
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None
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} else {
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Some(sr1)
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}
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)
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}
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/// Read Identification
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@ -385,7 +416,10 @@ impl Flash<Manual> {
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let args = Some(INST_WREN);
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self.transfer(args.into_iter(), 1);
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self.regs.gpio.modify(|_, w| w.wp_n(true));
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while !self.read_reg::<SR1>().wel() {}
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let sr1 = self.wait_while_sr1_zeroed();
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if !sr1.wel() {
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panic!("Cannot write-enable flash");
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}
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let result = f(self);
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@ -2,8 +2,7 @@ use bit_field::BitField;
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pub trait SpiFlashRegister {
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fn inst_code() -> u8;
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fn transfer_len() -> usize;
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fn new<I: Iterator<Item=u8>>(src: I) -> Self;
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fn new(src: u8) -> Self;
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}
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macro_rules! u8_register {
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@ -18,16 +17,18 @@ macro_rules! u8_register {
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$inst_code
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}
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fn transfer_len() -> usize {
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2
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}
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fn new<I: Iterator<Item=u8>>(mut src: I) -> Self {
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fn new(src: u8) -> Self {
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$name {
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inner: src.next().unwrap(),
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inner: src,
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}
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}
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}
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impl $name {
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pub fn is_zeroed(&self) -> bool {
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self.inner == 0
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}
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}
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};
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}
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