forked from M-Labs/zynq-rs
1
0
Fork 0

eth: begin phy communication

This commit is contained in:
Astro 2019-05-30 02:42:42 +02:00
parent 5b15bb5c0a
commit b13bf72c17
3 changed files with 74 additions and 1 deletions

View File

@ -1,6 +1,7 @@
use crate::regs::*; use crate::regs::*;
use crate::slcr; use crate::slcr;
pub mod phy;
mod regs; mod regs;
pub struct Eth { pub struct Eth {
@ -13,6 +14,7 @@ impl Eth {
// MDIO // MDIO
slcr.mio_pin_53.write( slcr.mio_pin_53.write(
slcr::MioPin53::zeroed() slcr::MioPin53::zeroed()
.tri_enable(true)
.l3_sel(0b100) .l3_sel(0b100)
.io_type(slcr::IoBufferType::Lvcmos18) .io_type(slcr::IoBufferType::Lvcmos18)
.pullup(true) .pullup(true)
@ -20,7 +22,6 @@ impl Eth {
// MDC // MDC
slcr.mio_pin_52.write( slcr.mio_pin_52.write(
slcr::MioPin52::zeroed() slcr::MioPin52::zeroed()
.tri_enable(true)
.l3_sel(0b100) .l3_sel(0b100)
.io_type(slcr::IoBufferType::Lvcmos18) .io_type(slcr::IoBufferType::Lvcmos18)
.pullup(true) .pullup(true)
@ -220,5 +221,54 @@ impl Eth {
.copy_all(true) .copy_all(true)
.mdc_clk_div(0b111) .mdc_clk_div(0b111)
); );
// TODO: mac addr
// TODO: Program the DMA Configuration register (gem.dma_cfg).
self.regs.net_ctrl.write(
regs::NetCtrl::zeroed()
.mgmt_port_en(true)
.tx_en(true)
.rx_en(true)
);
}
fn wait_phy_idle(&self) {
let mut timeout = 5_000_000;
while !self.regs.net_status.read().phy_mgmt_idle() {
timeout -= 1;
if timeout == 0 {
break
}
}
}
}
impl phy::PhyAccess for Eth {
fn read_phy(&mut self, addr: u8, reg: u8) -> u16 {
self.wait_phy_idle();
self.regs.phy_maint.write(
regs::PhyMaint::zeroed()
.clause_22(true)
.operation(regs::PhyOperation::Read)
.phy_addr(addr)
.reg_addr(reg)
.must_10(0b10)
);
self.wait_phy_idle();
self.regs.phy_maint.read().data()
}
fn write_phy(&mut self, addr: u8, reg: u8, data: u16) {
self.wait_phy_idle();
self.regs.phy_maint.write(
regs::PhyMaint::zeroed()
.clause_22(true)
.operation(regs::PhyOperation::Write)
.phy_addr(addr)
.reg_addr(reg)
.must_10(0b10)
.data(data)
);
self.wait_phy_idle();
} }
} }

8
src/eth/phy/mod.rs Normal file
View File

@ -0,0 +1,8 @@
pub trait PhyAccess {
fn read_phy(&mut self, addr: u8, reg: u8) -> u16;
fn write_phy(&mut self, addr: u8, reg: u8, data: u16);
}
pub trait PhyDevice {
fn init() -> Self;
}

View File

@ -124,7 +124,22 @@ impl RegisterBlock {
} }
register!(net_ctrl, NetCtrl, RW, u32); register!(net_ctrl, NetCtrl, RW, u32);
register_bit!(net_ctrl, loopback_local, 1);
register_bit!(net_ctrl, rx_en, 2);
register_bit!(net_ctrl, tx_en, 3);
register_bit!(net_ctrl, mgmt_port_en, 4);
register_bit!(net_ctrl, clear_stat_regs, 5); register_bit!(net_ctrl, clear_stat_regs, 5);
register_bit!(net_ctrl, incr_stat_regs, 6);
register_bit!(net_ctrl, wren_stat_regs, 7);
register_bit!(net_ctrl, back_pressure, 8);
register_bit!(net_ctrl, start_tx, 9);
register_bit!(net_ctrl, tx_halt, 10);
register_bit!(net_ctrl, tx_pause_frame, 11);
register_bit!(net_ctrl, tx_zeroq_pause_frame, 12);
register_bit!(net_ctrl, str_rx_timestamp, 15);
register_bit!(net_ctrl, en_pfc_pri_pause_rx, 16);
register_bit!(net_ctrl, tx_pfc_pri_pri_pause_frame, 17);
register_bit!(net_ctrl, flush_next_rx_dpram_pkt, 18);
register!(net_cfg, NetCfg, RW, u32); register!(net_cfg, NetCfg, RW, u32);
register_bit!(net_cfg, register_bit!(net_cfg,