forked from M-Labs/zynq-rs
libboard_zynq/slcr: fixed boot mode pins value
Notice that the bits in the table in UG585 are out of order.
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@ -590,16 +590,19 @@ register_bit!(a9_cpu_rst_ctrl, a9_rst0, 0);
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#[derive(Clone, Copy, Debug, PartialEq)]
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#[repr(u8)]
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pub enum BootModePins {
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// CAUTION!
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// The BOOT_MODE bits table 6-4 in UG585 are *out of order*.
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Jtag = 0b000,
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Nor = 0b001,
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Nand = 0b010,
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QuadSpi = 0b100,
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SdCard = 0b110,
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Nor = 0b010,
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Nand = 0b100,
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QuadSpi = 0b001,
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SdCard = 0b101,
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}
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register!(boot_mode, BootMode, RO, u32);
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register_bit!(boot_mode, pll_bypass, 4);
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register_bits_typed!(boot_mode, boot_mode_pins, u8, BootModePins, 0, 3);
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register_bit!(boot_mode, jtag_routing, 3);
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register_bits_typed!(boot_mode, boot_mode_pins, u8, BootModePins, 0, 2);
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register!(pss_rst_ctrl, PssRstCtrl, RW, u32);
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register_bit!(pss_rst_ctrl, soft_rst, 1);
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