forked from M-Labs/zynq-rs
add Red Pitaya support (WIP)
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@ -8,6 +8,7 @@ edition = "2018"
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[features]
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target_zc706 = ["libboard_zynq/target_zc706", "libsupport_zynq/target_zc706"]
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target_cora_z7_10 = ["libboard_zynq/target_cora_z7_10", "libsupport_zynq/target_cora_z7_10"]
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target_redpitaya = ["libboard_zynq/target_redpitaya", "libsupport_zynq/target_redpitaya"]
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default = ["target_zc706"]
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[dependencies]
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@ -109,6 +109,8 @@ pub fn main_core0() {
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const CPU_FREQ: u32 = 800_000_000;
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#[cfg(feature = "target_cora_z7_10")]
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const CPU_FREQ: u32 = 650_000_000;
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#[cfg(feature = "target_redpitaya")]
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const CPU_FREQ: u32 = 800_000_000;
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info!("Setup clock sources...");
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ArmPll::setup(2 * CPU_FREQ);
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@ -123,6 +125,11 @@ pub fn main_core0() {
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IoPll::setup(1_000_000_000);
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libboard_zynq::stdio::drop_uart();
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}
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#[cfg(feature = "target_redpitaya")]
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{
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IoPll::setup(1_000_000_000);
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libboard_zynq::stdio::drop_uart();
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}
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info!("PLLs set up");
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let clocks = zynq::clocks::Clocks::get();
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info!(
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@ -8,6 +8,7 @@ edition = "2018"
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[features]
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target_zc706 = []
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target_cora_z7_10 = []
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target_redpitaya = []
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ipv6 = [ "smoltcp/proto-ipv6" ]
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[dependencies]
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@ -6,6 +6,8 @@ use super::slcr;
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pub const PS_CLK: u32 = 33_333_333;
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#[cfg(feature = "target_cora_z7_10")]
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pub const PS_CLK: u32 = 50_000_000;
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#[cfg(feature = "target_redpitaya")]
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pub const PS_CLK: u32 = 33_333_333;
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/// (pll_fdiv_max, (pll_cp, pll_res, lock_cnt))
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const PLL_FDIV_LOCK_PARAM: &[(u16, (u8, u8, u16))] = &[
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@ -14,6 +14,10 @@ const DDR_FREQ: u32 = 666_666_666;
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/// Micron MT41K256M16HA-125: 800 MHz DDR3L, max supported 533 MHz
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const DDR_FREQ: u32 = 525_000_000;
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#[cfg(feature = "target_redpitaya")]
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/// Alliance Memory AS4C256M16D3B: 800 MHz DDR3
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const DDR_FREQ: u32 = 800_000_000;
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/// MT41K256M16HA-125
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const DCI_FREQ: u32 = 10_000_000;
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@ -147,6 +151,15 @@ impl DdrRam {
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.dci_type(slcr::DdriobDciType::Termination)
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.output_en(slcr::DdriobOutputEn::Obuf);
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#[cfg(feature = "target_cora_z7_10")]
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let data1_config = slcr::DdriobConfig::zeroed()
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.pullup_en(true);
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#[cfg(feature = "target_redpitaya")]
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let data0_config = slcr::DdriobConfig::zeroed()
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.inp_type(slcr::DdriobInputType::VrefDifferential)
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.term_en(true)
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.dci_type(slcr::DdriobDciType::Termination)
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.output_en(slcr::DdriobOutputEn::Obuf);
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#[cfg(feature = "target_redpitaya")]
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let data1_config = slcr::DdriobConfig::zeroed()
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.pullup_en(true);
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slcr.ddriob_data0.write(data0_config);
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@ -169,7 +182,15 @@ impl DdrRam {
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#[cfg(feature = "target_cora_z7_10")]
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let diff1_config = slcr::DdriobConfig::zeroed()
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.pullup_en(true);
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#[cfg(feature = "target_redpitaya")]
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let diff0_config = slcr::DdriobConfig::zeroed()
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.inp_type(slcr::DdriobInputType::Differential)
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.term_en(true)
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.dci_type(slcr::DdriobDciType::Termination)
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.output_en(slcr::DdriobOutputEn::Obuf);
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#[cfg(feature = "target_redpitaya")]
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let diff1_config = slcr::DdriobConfig::zeroed()
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.pullup_en(true);
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slcr.ddriob_diff0.write(diff0_config);
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slcr.ddriob_diff1.write(diff1_config);
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@ -200,6 +221,12 @@ impl DdrRam {
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.vref_ext_en_lower(false)
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.vref_ext_en_upper(false)
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);
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#[cfg(feature = "target_redpitaya")]
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slcr.ddriob_ddr_ctrl.modify(|_, w| w
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.vref_int_en(false)
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.vref_ext_en_lower(true)
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.vref_ext_en_upper(false)
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);
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});
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}
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@ -293,6 +320,8 @@ impl DdrRam {
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let width = regs::DataBusWidth::Width32bit;
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#[cfg(feature = "target_cora_z7_10")]
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let width = regs::DataBusWidth::Width16bit;
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#[cfg(feature = "target_redpitaya")]
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let width = regs::DataBusWidth::Width16bit;
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self.regs.ddrc_ctrl.modify(|_, w| w
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.soft_rstb(false)
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.powerdown_en(false)
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@ -322,6 +351,8 @@ impl DdrRam {
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let megabytes = 1023;
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#[cfg(feature = "target_cora_z7_10")]
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let megabytes = 511;
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#[cfg(feature = "target_redpitaya")]
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let megabytes = 511;
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megabytes * 1024 * 1024
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}
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@ -116,6 +116,18 @@ impl Sdio {
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.speed(true),
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);
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}
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// redpitaya card detect pin
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#[cfg(feature = "target_redpitaya")]
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{
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unsafe {
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slcr.sd0_wp_cd_sel.write(46 << 16);
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}
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slcr.mio_pin_46.write(
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slcr::MioPin46::zeroed()
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.io_type(slcr::IoBufferType::Lvcmos25)
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.speed(true),
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);
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}
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slcr.sdio_rst_ctrl.reset_sdio0();
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slcr.aper_clk_ctrl.enable_sdio0();
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slcr.sdio_clk_ctrl.enable_sdio0();
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@ -45,7 +45,7 @@ impl DerefMut for LazyUart {
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fn deref_mut(&mut self) -> &mut Uart {
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match self {
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LazyUart::Uninitialized => {
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#[cfg(feature = "target_cora_z7_10")]
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#[cfg(any(feature = "target_cora_z7_10", feature = "target_redpitaya"))]
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let uart = Uart::uart0(UART_RATE);
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#[cfg(feature = "target_zc706")]
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let uart = Uart::uart1(UART_RATE);
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@ -13,7 +13,7 @@ pub struct Uart {
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}
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impl Uart {
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#[cfg(feature = "target_cora_z7_10")]
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#[cfg(any(feature = "target_cora_z7_10", feature = "target_redpitaya"))]
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pub fn uart0(baudrate: u32) -> Self {
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slcr::RegisterBlock::unlocked(|slcr| {
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// Route UART 0 RxD/TxD Signals to MIO Pins
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@ -7,6 +7,7 @@ edition = "2018"
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[features]
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target_zc706 = []
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target_cora_z7_10 = []
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target_redpitaya = []
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power_saving = []
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default = ["target_zc706"]
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@ -8,6 +8,7 @@ edition = "2018"
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[features]
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target_zc706 = ["libboard_zynq/target_zc706"]
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target_cora_z7_10 = ["libboard_zynq/target_cora_z7_10"]
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target_redpitaya = ["libboard_zynq/target_redpitaya"]
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panic_handler = []
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dummy_irq_handler = []
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alloc_core = []
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@ -0,0 +1,12 @@
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# this is the original file from OpenOCD, but with ftdi_device_desc
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# removed because some cables don't have it programmed.
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# this supports JTAG-HS2 (and apparently Nexys4 as well)
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interface ftdi
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ftdi_vid_pid 0x0403 0x6014
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ftdi_channel 0
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ftdi_layout_init 0x00e8 0x60eb
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reset_config none
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@ -0,0 +1,38 @@
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source ./digilent-hs2.cfg
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adapter_khz 1000
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set PL_TAPID 0x13722093
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set SMP 1
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source ./zynq-7000.cfg
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reset_config none
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set XC7_JSHUTDOWN 0x0d
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set XC7_JPROGRAM 0x0b
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set XC7_JSTART 0x0c
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set XC7_BYPASS 0x3f
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proc xc7_program {tap} {
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global XC7_JSHUTDOWN XC7_JPROGRAM XC7_JSTART XC7_BYPASS
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irscan $tap $XC7_JSHUTDOWN
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irscan $tap $XC7_JPROGRAM
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runtest 60000
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#JSTART prevents this from working...
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#irscan $tap $XC7_JSTART
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runtest 2000
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irscan $tap $XC7_BYPASS
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runtest 2000
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}
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pld device virtex2 zynq.tap 1
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init
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xc7_program zynq.tap
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halt
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# Disable MMU
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targets $_TARGETNAME_1
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arm mcr 15 0 1 0 0 [expr [arm mrc 15 0 1 0 0] & ~0xd]
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targets $_TARGETNAME_0
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arm mcr 15 0 1 0 0 [expr [arm mrc 15 0 1 0 0] & ~0xd]
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