forked from M-Labs/zynq-rs
zynq::flash: begin driver implementation
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8037042040
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3180f1c3f7
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@ -0,0 +1,67 @@
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//! Quad-SPI Flash Controller
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use crate::regs::{RegisterW, RegisterRW};
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use super::slcr;
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use super::clocks::CpuClocks;
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pub mod regs;
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/// Flash Interface Driver
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pub struct Flash {
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regs: &'static mut regs::RegisterBlock,
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}
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impl Flash {
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pub fn new(clock: u32) -> Self {
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Self::enable_clocks(clock);
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Self::setup_signals();
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Self::reset();
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let regs = regs::RegisterBlock::qspi();
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let mut flash = Flash { regs };
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flash.configure();
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flash
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}
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fn enable_clocks(clock: u32) {
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let io_pll = CpuClocks::get().io;
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let divisor = ((clock - 1 + io_pll) / clock)
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.max(1).min(63) as u8;
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slcr::RegisterBlock::unlocked(|slcr| {
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slcr.lqspi_clk_ctrl.write(
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slcr::LqspiClkCtrl::zeroed()
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.src_sel(slcr::PllSource::IoPll)
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.divisor(divisor)
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.clkact(true)
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);
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});
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}
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fn setup_signals() {
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// TODO
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}
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fn reset() {
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slcr::RegisterBlock::unlocked(|slcr| {
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slcr.lqspi_rst_ctrl.write(
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slcr::LqspiRstCtrl::zeroed()
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.ref_rst(true)
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.cpu1x_rst(true)
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);
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slcr.lqspi_rst_ctrl.write(
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slcr::LqspiRstCtrl::zeroed()
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);
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});
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}
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fn configure(&mut self) {
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self.regs.config.modify(|_, w| w
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.baud_rate_div(4 /* TODO */)
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.mode_sel(true)
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.leg_flsh(true)
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.endian(false)
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.fifo_width(0b11)
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);
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}
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}
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@ -0,0 +1,78 @@
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use volatile_register::{RO, WO, RW};
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use crate::{register, register_bit, register_bits, register_bits_typed};
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#[repr(C)]
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pub struct RegisterBlock {
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pub config: Config,
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pub intr_status: RW<u32>,
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pub intr_en: RW<u32>,
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pub intr_dis: RW<u32>,
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pub intr_mask: RO<u32>,
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pub enable: RW<u32>,
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pub delay: RW<u32>,
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pub txd0: WO<u32>,
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pub rx_data: RO<u32>,
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pub slave_idle_count: RW<u32>,
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pub tx_thres: RW<u32>,
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pub rx_thes: RW<u32>,
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pub gpio: RW<u32>,
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pub _unused1: RO<u32>,
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pub lpbk_dly_adj: RW<u32>,
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pub _unused2: [RO<u32>; 17],
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pub txd1: WO<u32>,
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pub txd2: WO<u32>,
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pub txd3: WO<u32>,
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pub _unused3: [RO<u32>; 5],
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pub lqspi_cfg: RW<u32>,
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pub lqspi_sts: RW<u32>,
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pub _unused4: [RO<u32>; 21],
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pub mod_id: RW<u32>,
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}
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impl RegisterBlock {
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const BASE_ADDRESS: *mut Self = 0xE000D000 as *mut _;
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pub fn qspi() -> &'static mut Self {
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unsafe { &mut *Self::BASE_ADDRESS }
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}
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}
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register!(config, Config, RW, u32);
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register_bit!(config,
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/// Enables master mode
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mode_sel, 0);
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register_bit!(config,
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/// Clock polarity low/high
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clk_pol, 1);
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register_bit!(config,
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/// Clock phase
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clk_ph, 2);
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register_bits!(config,
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/// divisor = 2 ** (1 + baud_rate_div)
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baud_rate_div, u8, 3, 5);
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register_bits!(config,
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/// Must be set to 0b11
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fifo_width, u8, 6, 7);
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register_bit!(config,
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/// Must be 0
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ref_clk, 8);
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register_bit!(config,
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/// Peripheral Chip Select Line
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pcs, 10);
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register_bit!(config,
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/// false: auto mode, true: manual CS mode
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manual_cs, 14);
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register_bit!(config,
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/// false: auto mode, true: enables manual start enable
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man_start_en, 15);
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register_bit!(config,
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/// false: auto mode, true: enables manual start command
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man_start_com, 16);
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register_bit!(config, holdb_dr, 19);
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register_bit!(config,
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/// false: little, true: endian
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endian, 26);
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register_bit!(config,
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/// false: legacy SPI mode, true: Flash memory interface mode
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leg_flsh, 31);
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@ -6,3 +6,4 @@ pub mod axi_hp;
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pub mod axi_gp;
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pub mod ddr;
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pub mod mpcore;
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pub mod flash;
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@ -84,7 +84,7 @@ pub struct RegisterBlock {
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pub gem0_clk_ctrl: GemClkCtrl,
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pub gem1_clk_ctrl: GemClkCtrl,
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pub smc_clk_ctrl: RW<u32>,
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pub lqspi_clk_ctrl: RW<u32>,
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pub lqspi_clk_ctrl: LqspiClkCtrl,
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pub sdio_clk_ctrl: RW<u32>,
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pub uart_clk_ctrl: UartClkCtrl,
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pub spi_clk_ctrl: RW<u32>,
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@ -124,7 +124,7 @@ pub struct RegisterBlock {
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pub i2c_rst_ctrl: RW<u32>,
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pub uart_rst_ctrl: UartRstCtrl,
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pub gpio_rst_ctrl: RW<u32>,
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pub lqspi_rst_ctrl: RW<u32>,
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pub lqspi_rst_ctrl: LqspiRstCtrl,
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pub smc_rst_ctrl: RW<u32>,
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pub ocm_rst_ctrl: RW<u32>,
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reserved4: [u32; 1],
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@ -440,6 +440,15 @@ impl UartRstCtrl {
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}
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}
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register!(lqspi_clk_ctrl, LqspiClkCtrl, RW, u32);
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register_bit!(lqspi_clk_ctrl, clkact, 0);
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register_bits_typed!(lqspi_clk_ctrl, src_sel, u8, PllSource, 4, 5);
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register_bits!(lqspi_clk_ctrl, divisor, u8, 8, 13);
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register!(lqspi_rst_ctrl, LqspiRstCtrl, RW, u32);
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register_bit!(lqspi_rst_ctrl, ref_rst, 1);
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register_bit!(lqspi_rst_ctrl, cpu1x_rst, 0);
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register!(a9_cpu_rst_ctrl, A9CpuRstCtrl, RW, u32);
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register_bit!(a9_cpu_rst_ctrl, peri_rst, 8);
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register_bit!(a9_cpu_rst_ctrl, a9_clkstop1, 5);
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