delint

src/cortex_a9/mmu.rs

@@ -1,4 +1,3 @@
-use core::mem::uninitialized;
 use bit_field::BitField;
 use super::{regs::*, asm};
 use crate::regs::RegisterW;
@@ -73,7 +72,7 @@ pub struct L1Entry(u32);
 impl L1Entry {
     #[inline(always)]
     pub fn section(phys_base: u32, section: L1Section) -> Self {
-        /// Must be aligned to 1 MB
+        // Must be aligned to 1 MB
         assert!(phys_base & 0x000f_ffff == 0);
         let mut entry = L1Entry(phys_base);
 
@@ -382,8 +381,4 @@ pub fn with_mmu<F: FnMut() -> !>(l1table: &L1Table, mut f: F) -> ! {
     asm::isb();
 
     f();
-
-    // table must live until here
-    drop(l1table.table);
-    unreachable!();
 }

src/cortex_a9/regs.rs

@@ -1,5 +1,5 @@
 use crate::{register_bit, register_bits};
-use crate::regs::{RegisterR, RegisterW, RegisterRW};
+use crate::regs::{RegisterR, RegisterW};
 
 macro_rules! def_reg_r {
     ($name:tt, $type: ty, $asm_instr:tt) => {

src/eth/mod.rs

@@ -219,7 +219,7 @@ impl<RX, TX> Eth<RX, TX> {
         });
     }
 
-    fn init(mut self) -> Self {
+    fn init(self) -> Self {
         // Clear the Network Control register.
         self.regs.net_ctrl.write(regs::NetCtrl::zeroed());
         self.regs.net_ctrl.write(regs::NetCtrl::zeroed().clear_stat_regs(true));

src/eth/regs.rs

@@ -1,6 +1,6 @@
 use volatile_register::{RO, WO, RW};
 
-use crate::{register, register_bit, register_bits, register_bits_typed, regs::*};
+use crate::{register, register_bit, register_bits, register_bits_typed};
 
 #[repr(C)]
 pub struct RegisterBlock {

src/eth/rx.rs

@@ -1,5 +1,5 @@
 use core::ops::Deref;
-use crate::{register, register_bit, register_bits, register_bits_typed, regs::*};
+use crate::{register, register_bit, register_bits, regs::*};
 use super::MTU;
 
 #[derive(Debug)]
@@ -18,10 +18,12 @@ pub struct DescEntry {
 }
 
 register!(desc_word0, DescWord0, RW, u32);
+register_bit!(desc_word0,
               /// true if owned by software, false if owned by hardware
-register_bit!(desc_word0, used, 0);
+              used, 0);
+register_bit!(desc_word0,
               /// mark last desc in list
-register_bit!(desc_word0, wrap, 1);
+              wrap, 1);
 register_bits!(desc_word0, address, u32, 2, 31);
 
 register!(desc_word1, DescWord1, RW, u32);

src/eth/tx.rs

@@ -1,5 +1,5 @@
 use core::ops::{Deref, DerefMut};
-use crate::{register, register_bit, register_bits, register_bits_typed, regs::*};
+use crate::{register, register_bit, register_bits, regs::*};
 use crate::println;
 use super::{MTU, regs};
 
@@ -20,10 +20,12 @@ register_bits!(desc_word1, csum_offload_errors, u8, 20, 22);
 register_bit!(desc_word1, late_collision_tx_error, 26);
 register_bit!(desc_word1, ahb_frame_corruption, 27);
 register_bit!(desc_word1, retry_limit_exceeded, 29);
+register_bit!(desc_word1,
               /// marks last descriptor in list
-register_bit!(desc_word1, wrap, 30);
+              wrap, 30);
+register_bit!(desc_word1,
               /// true if owned by software, false if owned by hardware
-register_bit!(desc_word1, used, 31);
+              used, 31);
 
 /// Number of descriptors
 pub const DESCS: usize = 8;

src/main.rs

@@ -5,6 +5,8 @@
 #![feature(naked_functions)]
 #![feature(compiler_builtins_lib)]
 #![feature(never_type)]
+// TODO: disallow unused/dead_code when code moves into a lib crate
+#![allow(dead_code)]
 
 use core::mem::uninitialized;
 
@@ -79,7 +81,7 @@ fn main() {
 
     let mut rx_descs: [eth::rx::DescEntry; 8] = unsafe { uninitialized() };
     let mut rx_buffers = [[0u8; 1536]; 8];
-    let mut eth = eth.start_rx(&mut rx_descs, &mut rx_buffers);
+    let eth = eth.start_rx(&mut rx_descs, &mut rx_buffers);
     let mut tx_descs: [eth::tx::DescEntry; 8] = unsafe { uninitialized() };
     let mut tx_buffers = [[0u8; 1536]; 8];
     let mut eth = eth.start_tx(&mut tx_descs, &mut tx_buffers);
@@ -111,7 +113,6 @@ fn main() {
             None => println!("eth tx shortage"),
         }
     }
-    panic!("End");
 }
 
 #[panic_handler]

src/slcr.rs

@@ -1,6 +1,6 @@
 ///! Register definitions for System Level Control
 
-use volatile_register::{RO, WO, RW};
+use volatile_register::{RO, RW};
 use crate::{register, register_at,
             register_bit, register_bits, register_bits_typed,
             regs::RegisterW, regs::RegisterRW};

src/stdio.rs

@@ -9,7 +9,7 @@ pub fn get_uart() -> &'static mut Uart {
     unsafe {
         match &mut UART {
             None => {
-                let mut uart = Uart::serial(UART_RATE);
+                let uart = Uart::serial(UART_RATE);
                 UART = Some(uart);
                 UART.as_mut().unwrap()
             }
@@ -23,7 +23,7 @@ macro_rules! print {
     ($($arg:tt)*) => ({
         use core::fmt::Write;
         let uart = crate::stdio::get_uart();
-        write!(uart, $($arg)*);
+        let _ = write!(uart, $($arg)*);
     })
 }
 
@@ -32,8 +32,8 @@ macro_rules! println {
     ($($arg:tt)*) => ({
         use core::fmt::Write;
         let uart = crate::stdio::get_uart();
-        write!(uart, $($arg)*);
-        write!(uart, "\r\n");
+        let _ = write!(uart, $($arg)*);
+        let _ = write!(uart, "\r\n");
         while !uart.tx_fifo_empty() {}
     })
 }

src/uart/baud_rate_gen.rs

@@ -37,7 +37,7 @@ pub fn configure(regs: &mut RegisterBlock, mut clk: u32, baud: u32) {
     }
 
     match best {
-        Some((cd, bdiv, error)) => {
+        Some((cd, bdiv, _error)) => {
             regs.baud_rate_gen.write(BaudRateGen::zeroed().cd(cd));
             regs.baud_rate_divider.write(BaudRateDiv::zeroed().bdiv(bdiv));
         }

src/uart/mod.rs

@@ -1,5 +1,4 @@
 use core::fmt;
-use volatile_register::RW;
 
 use crate::regs::*;
 use crate::slcr;

src/uart/regs.rs

@@ -1,6 +1,6 @@
 use volatile_register::{RO, WO, RW};
 
-use crate::{register, register_bit, register_bits, register_bits_typed, register_at, regs::*};
+use crate::{register, register_bit, register_bits, register_bits_typed, register_at};
 
 #[repr(u8)]
 pub enum ChannelMode {