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eth::phy: replace ExtendedStatus with PSSR

This commit is contained in:
Astro 2020-07-29 21:49:18 +02:00
parent e408a8b22d
commit 1f05e6977e
4 changed files with 62 additions and 82 deletions

View File

@ -610,17 +610,15 @@ impl<GEM: Gem> EthInner<GEM> {
Some(link) => { Some(link) => {
info!("eth: got {:?}", link); info!("eth: got {:?}", link);
use phy::LinkSpeed::*; use phy::{LinkDuplex::Full, LinkSpeed::*};
let txclock = match link.speed { let txclock = match link.speed {
S10 => TX_10, S10 => TX_10,
S100 => TX_100, S100 => TX_100,
S1000 => TX_1000, S1000 => TX_1000,
}; };
GEM::setup_clock(txclock); GEM::setup_clock(txclock);
/* .full_duplex(false) doesn't work even if
half duplex has been negotiated. */
GEM::regs().net_cfg.modify(|_, w| w GEM::regs().net_cfg.modify(|_, w| w
.full_duplex(true) .full_duplex(link.duplex == Full)
.gige_en(link.speed == S1000) .gige_en(link.speed == S1000)
.speed(link.speed != S10) .speed(link.speed != S10)
); );

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@ -1,59 +0,0 @@
use bit_field::BitField;
use super::{PhyRegister, Link, LinkDuplex, LinkSpeed};
#[derive(Clone, Copy, Debug)]
/// 1000Base-T Extended Status Register
pub struct ExtendedStatus(pub u16);
impl ExtendedStatus {
pub fn cap_1000base_t_half(&self) -> bool {
self.0.get_bit(12)
}
pub fn cap_1000base_t_full(&self) -> bool {
self.0.get_bit(13)
}
pub fn cap_1000base_x_half(&self) -> bool {
self.0.get_bit(14)
}
pub fn cap_1000base_x_full(&self) -> bool {
self.0.get_bit(15)
}
pub fn get_link(&self) -> Option<Link> {
if self.cap_1000base_t_half() {
Some(Link {
speed: LinkSpeed::S1000,
duplex: LinkDuplex::Half,
})
} else if self.cap_1000base_t_full() {
Some(Link {
speed: LinkSpeed::S1000,
duplex: LinkDuplex::Full,
})
} else if self.cap_1000base_x_half() {
Some(Link {
speed: LinkSpeed::S1000,
duplex: LinkDuplex::Half,
})
} else if self.cap_1000base_x_full() {
Some(Link {
speed: LinkSpeed::S1000,
duplex: LinkDuplex::Full,
})
} else {
None
}
}
}
impl PhyRegister for ExtendedStatus {
fn addr() -> u8 {
0xF
}
}
impl From<u16> for ExtendedStatus {
fn from(value: u16) -> Self {
ExtendedStatus(value)
}
}

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@ -2,10 +2,10 @@ pub mod id;
use id::{identify_phy, PhyIdentifier}; use id::{identify_phy, PhyIdentifier};
mod status; mod status;
pub use status::Status; pub use status::Status;
mod extended_status;
pub use extended_status::ExtendedStatus;
mod control; mod control;
pub use control::Control; pub use control::Control;
mod pssr;
pub use pssr::PSSR;
#[derive(Clone, Debug, PartialEq)] #[derive(Clone, Debug, PartialEq)]
pub struct Link { pub struct Link {
@ -49,8 +49,8 @@ const OUI_REALTEK: u32 = 0x000732;
impl Phy { impl Phy {
/// Probe all addresses on MDIO for a known PHY /// Probe all addresses on MDIO for a known PHY
pub fn find<PA: PhyAccess>(pa: &mut PA) -> Option<Phy> { pub fn find<PA: PhyAccess>(pa: &mut PA) -> Option<Phy> {
for addr in 1..32 { (1..32).filter_map(|addr| {
let device = match identify_phy(pa, addr) { match identify_phy(pa, addr) {
Some(PhyIdentifier { Some(PhyIdentifier {
oui: OUI_MARVELL, oui: OUI_MARVELL,
model: 36, model: 36,
@ -62,15 +62,8 @@ impl Phy {
rev: 0b0101, rev: 0b0101,
}) => Some(PhyDevice::Rtl8211E), }) => Some(PhyDevice::Rtl8211E),
_ => None, _ => None,
}; }.map(|device| Phy { addr, device })
match device { }).next()
Some(device) =>
return Some(Phy { addr, device }),
None => {}
}
}
None
} }
pub fn name(&self) -> &'static str { pub fn name(&self) -> &'static str {
@ -120,12 +113,8 @@ impl Phy {
if !status.link_status() { if !status.link_status() {
None None
} else if status.cap_1000base_t_extended_status() { } else if status.cap_1000base_t_extended_status() {
let ext_status: ExtendedStatus = self.read_reg(pa); let phy_status: PSSR = self.read_reg(pa);
if let Some(link) = ext_status.get_link() { phy_status.get_link()
Some(link)
} else {
status.get_link()
}
} else { } else {
status.get_link() status.get_link()
} }

View File

@ -0,0 +1,52 @@
use bit_field::BitField;
use super::{PhyRegister, Link, LinkDuplex, LinkSpeed};
#[derive(Clone, Copy, Debug)]
/// PHY-Specific Status Register
pub struct PSSR(pub u16);
impl PSSR {
pub fn link(&self) -> bool {
self.0.get_bit(10)
}
pub fn duplex(&self) -> LinkDuplex {
if self.0.get_bit(13) {
LinkDuplex::Full
} else {
LinkDuplex::Half
}
}
pub fn speed(&self) -> Option<LinkSpeed> {
match self.0.get_bits(14..=15) {
0b00 => Some(LinkSpeed::S10),
0b01 => Some(LinkSpeed::S100),
0b10 => Some(LinkSpeed::S1000),
_ => None,
}
}
pub fn get_link(&self) -> Option<Link> {
if self.link() {
Some(Link {
speed: self.speed()?,
duplex: self.duplex(),
})
} else {
None
}
}
}
impl PhyRegister for PSSR {
fn addr() -> u8 {
0x11
}
}
impl From<u16> for PSSR {
fn from(value: u16) -> Self {
PSSR(value)
}
}