forked from M-Labs/zynq-rs
pca954x: fix to work on cold boot
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bc41b91192
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14b0247716
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@ -144,27 +144,26 @@ impl I2c {
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}
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#[cfg(feature = "target_kasli_soc")]
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fn pca_autodetect(&mut self) -> Result<PCA954X, &'static str> {
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pub fn pca_autodetect(&mut self) -> Result<PCA954X, &'static str> {
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// start with resetting the PCA954X
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self.i2cswr_oe(false);
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self.i2cswr_o(false);
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self.delay_us(10); // reset time is just 500ns
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self.i2cswr_oe(true);
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self.i2cswr_o(true);
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self.delay_us(10);
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let pca954x_addr = 0x71;
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/*self.i2cswr_oe(false);
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self.unit_delay();
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self.i2cswr_oe(true);*/
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let pca954x_read_addr = (0x71 << 1) | 0x01;
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self.start()?;
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// read the config register
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if !self.write(pca954x_addr)? {
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if !self.write(pca954x_read_addr)? {
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return Err("PCA954X failed to ack read address");
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}
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let config = self.read(true)?;
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let config = self.read(false)?;
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let pca = match config {
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0x00 => PCA954X::PCA9548,
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0x08 => PCA954X::PCA9547,
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_ => { return Err("Unknown PCA954X type."); }
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_ => { return Err("Unknown response for PCA954X autodetect")},
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};
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self.stop()?;
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Ok(pca)
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@ -196,14 +195,13 @@ impl I2c {
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return Err("SCL is stuck low");
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}
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// postcondition: SCL and SDA high
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#[cfg(feature = "target_kasli_soc")]
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{
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self.unit_delay();
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self.pca_type = self.pca_autodetect()?;
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}
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#[cfg(not(feature = "target_kasli_soc"))]
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{
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self.pca_type = PCA954X::PCA9548;
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}
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Ok(())
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}
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@ -287,7 +285,7 @@ impl I2c {
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if self.sda_i() { data |= 1 << bit }
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self.scl_oe(true);
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}
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// Send ack/nack
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// Send ack/nack (true = nack, false = ack)
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self.sda_oe(ack);
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self.unit_delay();
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self.scl_oe(false);
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@ -76,7 +76,7 @@ register_bit!(gpio_output_mask_lower,
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i2cswr_o, 1);
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#[cfg(feature = "target_kasli_soc")]
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register_bits!(gpio_output_mask_lower,
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mask, u16, 16, 31);
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mask, u16, 16, 31);
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register!(gpio_input,
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/// DATA_1_RO:
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