morgan
/
zynq-rs
forked from M-Labs/zynq-rs
1
0
Fork 0
Code Pull Requests Activity

rename target_cora_z7_10 to target_coraz7 globally

This commit is contained in:
Astro 2020-11-13 17:56:47 +01:00
parent 5b2c779cba
commit 0714162113
14 changed files with 28 additions and 28 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
README.md
View File

@ -38,7 +38,7 @@ openocd -f zc706.cfg
### Running on the Cora Z7-10 ### Running on the Cora Z7-10
```shell ```shell
nix-shell --command "cd experiments && cargo xbuild --release --no-default-features --features=target_cora_z7_10" nix-shell --command "cd experiments && cargo xbuild --release --no-default-features --features=target_coraz7"
cd openocd cd openocd
openocd -f cora-z7-10.cfg openocd -f cora-z7-10.cfg
``` ```

2
experiments/Cargo.toml
View File

@ -7,7 +7,7 @@ edition = "2018"
[features] [features]
target_zc706 = ["libboard_zynq/target_zc706", "libsupport_zynq/target_zc706"] target_zc706 = ["libboard_zynq/target_zc706", "libsupport_zynq/target_zc706"]
target_cora_z7_10 = ["libboard_zynq/target_cora_z7_10", "libsupport_zynq/target_cora_z7_10"] target_coraz7 = ["libboard_zynq/target_coraz7", "libsupport_zynq/target_coraz7"]
target_redpitaya = ["libboard_zynq/target_redpitaya", "libsupport_zynq/target_redpitaya"] target_redpitaya = ["libboard_zynq/target_redpitaya", "libsupport_zynq/target_redpitaya"]
default = ["target_zc706"] default = ["target_zc706"]

4
experiments/src/main.rs
View File

@ -107,7 +107,7 @@ pub fn main_core0() {
#[cfg(feature = "target_zc706")] #[cfg(feature = "target_zc706")]
const CPU_FREQ: u32 = 800_000_000; const CPU_FREQ: u32 = 800_000_000;
#[cfg(feature = "target_cora_z7_10")] #[cfg(feature = "target_coraz7")]
const CPU_FREQ: u32 = 650_000_000; const CPU_FREQ: u32 = 650_000_000;
#[cfg(feature = "target_redpitaya")] #[cfg(feature = "target_redpitaya")]
const CPU_FREQ: u32 = 800_000_000; const CPU_FREQ: u32 = 800_000_000;
@ -120,7 +120,7 @@ pub fn main_core0() {
IoPll::setup(1_000_000_000); IoPll::setup(1_000_000_000);
libboard_zynq::stdio::drop_uart(); libboard_zynq::stdio::drop_uart();
} }
#[cfg(feature = "target_cora_z7_10")] #[cfg(feature = "target_coraz7")]
{ {
IoPll::setup(1_000_000_000); IoPll::setup(1_000_000_000);
libboard_zynq::stdio::drop_uart(); libboard_zynq::stdio::drop_uart();

2
libboard_zynq/Cargo.toml
View File

@ -7,7 +7,7 @@ edition = "2018"
[features] [features]
target_zc706 = [] target_zc706 = []
target_cora_z7_10 = [] target_coraz7 = []
target_redpitaya = [] target_redpitaya = []
ipv6 = [ "smoltcp/proto-ipv6" ] ipv6 = [ "smoltcp/proto-ipv6" ]

2
libboard_zynq/src/clocks/source.rs
View File

@ -4,7 +4,7 @@ use super::slcr;
#[cfg(feature = "target_zc706")] #[cfg(feature = "target_zc706")]
pub const PS_CLK: u32 = 33_333_333; pub const PS_CLK: u32 = 33_333_333;
#[cfg(feature = "target_cora_z7_10")] #[cfg(feature = "target_coraz7")]
pub const PS_CLK: u32 = 50_000_000; pub const PS_CLK: u32 = 50_000_000;
#[cfg(feature = "target_redpitaya")] #[cfg(feature = "target_redpitaya")]
pub const PS_CLK: u32 = 33_333_333; pub const PS_CLK: u32 = 33_333_333;

26
libboard_zynq/src/ddr/mod.rs
View File

@ -12,7 +12,7 @@ mod regs;
/// Micron MT41J256M8HX-15E: 667 MHz DDR3 /// Micron MT41J256M8HX-15E: 667 MHz DDR3
const DDR_FREQ: u32 = 666_666_666; const DDR_FREQ: u32 = 666_666_666;
#[cfg(feature = "target_cora_z7_10")] #[cfg(feature = "target_coraz7")]
/// Micron MT41K256M16HA-125: 800 MHz DDR3L, max supported 533 MHz /// Micron MT41K256M16HA-125: 800 MHz DDR3L, max supported 533 MHz
const DDR_FREQ: u32 = 525_000_000; const DDR_FREQ: u32 = 525_000_000;
@ -144,13 +144,13 @@ impl DdrRam {
.output_en(slcr::DdriobOutputEn::Obuf); .output_en(slcr::DdriobOutputEn::Obuf);
#[cfg(feature = "target_zc706")] #[cfg(feature = "target_zc706")]
let data1_config = data0_config.clone(); let data1_config = data0_config.clone();
#[cfg(feature = "target_cora_z7_10")] #[cfg(feature = "target_coraz7")]
let data0_config = slcr::DdriobConfig::zeroed() let data0_config = slcr::DdriobConfig::zeroed()
.inp_type(slcr::DdriobInputType::VrefDifferential) .inp_type(slcr::DdriobInputType::VrefDifferential)
.term_en(true) .term_en(true)
.dci_type(slcr::DdriobDciType::Termination) .dci_type(slcr::DdriobDciType::Termination)
.output_en(slcr::DdriobOutputEn::Obuf); .output_en(slcr::DdriobOutputEn::Obuf);
#[cfg(feature = "target_cora_z7_10")] #[cfg(feature = "target_coraz7")]
let data1_config = slcr::DdriobConfig::zeroed() let data1_config = slcr::DdriobConfig::zeroed()
.pullup_en(true); .pullup_en(true);
#[cfg(feature = "target_redpitaya")] #[cfg(feature = "target_redpitaya")]
@ -173,13 +173,13 @@ impl DdrRam {
.output_en(slcr::DdriobOutputEn::Obuf); .output_en(slcr::DdriobOutputEn::Obuf);
#[cfg(feature = "target_zc706")] #[cfg(feature = "target_zc706")]
let diff1_config = diff0_config.clone(); let diff1_config = diff0_config.clone();
#[cfg(feature = "target_cora_z7_10")] #[cfg(feature = "target_coraz7")]
let diff0_config = slcr::DdriobConfig::zeroed() let diff0_config = slcr::DdriobConfig::zeroed()
.inp_type(slcr::DdriobInputType::Differential) .inp_type(slcr::DdriobInputType::Differential)
.term_en(true) .term_en(true)
.dci_type(slcr::DdriobDciType::Termination) .dci_type(slcr::DdriobDciType::Termination)
.output_en(slcr::DdriobOutputEn::Obuf); .output_en(slcr::DdriobOutputEn::Obuf);
#[cfg(feature = "target_cora_z7_10")] #[cfg(feature = "target_coraz7")]
let diff1_config = slcr::DdriobConfig::zeroed() let diff1_config = slcr::DdriobConfig::zeroed()
.pullup_en(true); .pullup_en(true);
#[cfg(feature = "target_redpitaya")] #[cfg(feature = "target_redpitaya")]
@ -207,7 +207,7 @@ impl DdrRam {
slcr.ddriob_drive_slew_clock.write(0x00F9861C); slcr.ddriob_drive_slew_clock.write(0x00F9861C);
} }
#[cfg(feature = "target_cora_z7_10")] #[cfg(feature = "target_coraz7")]
slcr.ddriob_ddr_ctrl.modify(|_, w| w slcr.ddriob_ddr_ctrl.modify(|_, w| w
.vref_int_en(false) .vref_int_en(false)
.vref_ext_en_lower(true) .vref_ext_en_lower(true)
@ -232,7 +232,7 @@ impl DdrRam {
} }
fn configure(&mut self) { fn configure(&mut self) {
#[cfg(feature = "target_cora_z7_10")] #[cfg(feature = "target_coraz7")]
self.regs.dram_param0.write( self.regs.dram_param0.write(
regs::DramParam0::zeroed() regs::DramParam0::zeroed()
.t_rc(0x1a) .t_rc(0x1a)
@ -295,11 +295,11 @@ impl DdrRam {
.emr(0x4) .emr(0x4)
); );
#[cfg(feature = "target_cora_z7_10")] #[cfg(feature = "target_coraz7")]
self.regs.phy_configs[2].modify( self.regs.phy_configs[2].modify(
|_, w| w.data_slice_in_use(false) |_, w| w.data_slice_in_use(false)
); );
#[cfg(feature = "target_cora_z7_10")] #[cfg(feature = "target_coraz7")]
self.regs.phy_configs[3].modify( self.regs.phy_configs[3].modify(
|_, w| w.data_slice_in_use(false) |_, w| w.data_slice_in_use(false)
); );
@ -351,7 +351,7 @@ impl DdrRam {
.gatelvl_init_ratio(0xee) .gatelvl_init_ratio(0xee)
); );
#[cfg(feature = "target_cora_z7_10")] #[cfg(feature = "target_coraz7")]
self.regs.reg_64.modify( self.regs.reg_64.modify(
|_, w| w |_, w| w
.phy_ctrl_slave_ratio(0x100) .phy_ctrl_slave_ratio(0x100)
@ -387,7 +387,7 @@ impl DdrRam {
fn reset_ddrc<F: FnMut(&mut Self)>(&mut self, mut f: F) { fn reset_ddrc<F: FnMut(&mut Self)>(&mut self, mut f: F) {
#[cfg(feature = "target_zc706")] #[cfg(feature = "target_zc706")]
let width = regs::DataBusWidth::Width32bit; let width = regs::DataBusWidth::Width32bit;
#[cfg(feature = "target_cora_z7_10")] #[cfg(feature = "target_coraz7")]
let width = regs::DataBusWidth::Width16bit; let width = regs::DataBusWidth::Width16bit;
#[cfg(feature = "target_redpitaya")] #[cfg(feature = "target_redpitaya")]
let width = regs::DataBusWidth::Width16bit; let width = regs::DataBusWidth::Width16bit;
@ -405,7 +405,7 @@ impl DdrRam {
self.regs.dram_addr_map_col.write(0xFFF00000); self.regs.dram_addr_map_col.write(0xFFF00000);
self.regs.dram_addr_map_row.write(0x0F666666); self.regs.dram_addr_map_row.write(0x0F666666);
} }
#[cfg(any(feature = "target_cora_z7_10", feature = "target_redpitaya"))] #[cfg(any(feature = "target_coraz7", feature = "target_redpitaya"))]
unsafe { unsafe {
// row/column address bits // row/column address bits
self.regs.dram_addr_map_bank.write(0x00000666); self.regs.dram_addr_map_bank.write(0x00000666);
@ -437,7 +437,7 @@ impl DdrRam {
// filtering address map // filtering address map
#[cfg(feature = "target_zc706")] #[cfg(feature = "target_zc706")]
let megabytes = 1023; let megabytes = 1023;
#[cfg(feature = "target_cora_z7_10")] #[cfg(feature = "target_coraz7")]
let megabytes = 512; let megabytes = 512;
#[cfg(feature = "target_redpitaya")] #[cfg(feature = "target_redpitaya")]
let megabytes = 512; let megabytes = 512;

2
libboard_zynq/src/sdio/mod.rs
View File

@ -105,7 +105,7 @@ impl Sdio {
); );
} }
// cora card detect pin // cora card detect pin
#[cfg(feature = "target_cora_z7_10")] #[cfg(feature = "target_coraz7")]
{ {
unsafe { unsafe {
slcr.sd0_wp_cd_sel.write(47 << 16); slcr.sd0_wp_cd_sel.write(47 << 16);

2
libboard_zynq/src/stdio.rs
View File

@ -45,7 +45,7 @@ impl DerefMut for LazyUart {
fn deref_mut(&mut self) -> &mut Uart { fn deref_mut(&mut self) -> &mut Uart {
match self { match self {
LazyUart::Uninitialized => { LazyUart::Uninitialized => {
#[cfg(any(feature = "target_cora_z7_10", feature = "target_redpitaya"))] #[cfg(any(feature = "target_coraz7", feature = "target_redpitaya"))]
let uart = Uart::uart0(UART_RATE); let uart = Uart::uart0(UART_RATE);
#[cfg(feature = "target_zc706")] #[cfg(feature = "target_zc706")]
let uart = Uart::uart1(UART_RATE); let uart = Uart::uart1(UART_RATE);

2
libboard_zynq/src/uart/mod.rs
View File

@ -13,7 +13,7 @@ pub struct Uart {
} }
impl Uart { impl Uart {
#[cfg(any(feature = "target_cora_z7_10", feature = "target_redpitaya"))] #[cfg(any(feature = "target_coraz7", feature = "target_redpitaya"))]
pub fn uart0(baudrate: u32) -> Self { pub fn uart0(baudrate: u32) -> Self {
slcr::RegisterBlock::unlocked(|slcr| { slcr::RegisterBlock::unlocked(|slcr| {
// Route UART 0 RxD/TxD Signals to MIO Pins // Route UART 0 RxD/TxD Signals to MIO Pins

2
libconfig/Cargo.toml
View File

@ -12,6 +12,6 @@ log = "0.4"
[features] [features]
target_zc706 = [] target_zc706 = []
target_cora_z7_10 = [] target_coraz7 = []
target_redpitaya = [] target_redpitaya = []
ipv6 = [] ipv6 = []

4
libconfig/src/net_settings.rs
View File

@ -35,9 +35,9 @@ pub fn get_adresses(cfg: &Config) -> NetAddresses {
let mut hardware_addr = EthernetAddress([0x02, 0x00, 0x00, 0x00, 0x00, 0x52]); let mut hardware_addr = EthernetAddress([0x02, 0x00, 0x00, 0x00, 0x00, 0x52]);
#[cfg(feature = "target_zc706")] #[cfg(feature = "target_zc706")]
let mut ipv4_addr = IpAddress::v4(192, 168, 1, 52); let mut ipv4_addr = IpAddress::v4(192, 168, 1, 52);
#[cfg(feature = "target_cora_z7_10")] #[cfg(feature = "target_coraz7")]
let mut hardware_addr = EthernetAddress([0x02, 0x00, 0x00, 0x00, 0x00, 0x54]); let mut hardware_addr = EthernetAddress([0x02, 0x00, 0x00, 0x00, 0x00, 0x54]);
#[cfg(feature = "target_cora_z7_10")] #[cfg(feature = "target_coraz7")]
let mut ipv4_addr = IpAddress::v4(192, 168, 1, 54); let mut ipv4_addr = IpAddress::v4(192, 168, 1, 54);
#[cfg(feature = "target_redpitaya")] #[cfg(feature = "target_redpitaya")]
let mut hardware_addr = EthernetAddress([0x02, 0x00, 0x00, 0x00, 0x00, 0x55]); let mut hardware_addr = EthernetAddress([0x02, 0x00, 0x00, 0x00, 0x00, 0x55]);

2
libcortex_a9/Cargo.toml
View File

@ -6,7 +6,7 @@ edition = "2018"
[features] [features]
target_zc706 = [] target_zc706 = []
target_cora_z7_10 = [] target_coraz7 = []
target_redpitaya = [] target_redpitaya = []
power_saving = [] power_saving = []
default = ["target_zc706"] default = ["target_zc706"]

2
libsupport_zynq/Cargo.toml
View File

@ -7,7 +7,7 @@ edition = "2018"
[features] [features]
target_zc706 = ["libboard_zynq/target_zc706"] target_zc706 = ["libboard_zynq/target_zc706"]
target_cora_z7_10 = ["libboard_zynq/target_cora_z7_10"] target_coraz7 = ["libboard_zynq/target_coraz7"]
target_redpitaya = ["libboard_zynq/target_redpitaya"] target_redpitaya = ["libboard_zynq/target_redpitaya"]
panic_handler = [] panic_handler = []
dummy_irq_handler = [] dummy_irq_handler = []

2
szl/Cargo.toml
View File

@ -7,7 +7,7 @@ edition = "2018"
[features] [features]
target_zc706 = ["libboard_zynq/target_zc706", "libsupport_zynq/target_zc706", "libconfig/target_zc706"] target_zc706 = ["libboard_zynq/target_zc706", "libsupport_zynq/target_zc706", "libconfig/target_zc706"]
target_cora_z7_10 = ["libboard_zynq/target_cora_z7_10", "libsupport_zynq/target_cora_z7_10", "libconfig/target_cora_z7_10"] target_coraz7 = ["libboard_zynq/target_coraz7", "libsupport_zynq/target_coraz7", "libconfig/target_coraz7"]
target_redpitaya = ["libboard_zynq/target_redpitaya", "libsupport_zynq/target_redpitaya", "libconfig/target_redpitaya"] target_redpitaya = ["libboard_zynq/target_redpitaya", "libsupport_zynq/target_redpitaya", "libconfig/target_redpitaya"]
default = ["target_zc706"] default = ["target_zc706"]