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bors[bot] 0eda3c511c
Merge #32 
32: add user trap setup and handling registers r=almindor a=almindor

Adds CSR handlers for user trap setup and handling registers.

Also unifies common shared types.

NOTE: untested, will test on real device ASAP

Co-authored-by: Ales Katona <almindor@gmail.com>
 		2019-09-13 21:15:02 +00:00
.github A unified contributing experience. 2018-08-12 08:59:12 +02:00
bin add riscv32i target 2019-07-26 00:13:38 +08:00
ci Enable gcc caching 2019-03-17 17:24:07 +03:00
src ucause only as readable bits 2019-08-31 17:32:43 -06:00
.gitignore Implement asm functions 2019-01-23 01:29:54 +03:00
.travis.yml Add MSRV policy 2019-03-17 17:29:48 +03:00
CODE_OF_CONDUCT.md Rename RISCV to RISC-V 2019-03-28 18:31:57 +01:00
Cargo.toml Do not use bare-metal v0.2.5 (changes MSRV) 2019-09-05 19:53:02 +03:00
README.md Rename RISCV to RISC-V 2019-03-28 18:31:57 +01:00
asm.S Declare all the CSR registers in asm.S 2019-06-25 23:33:40 +03:00
asm.h Declare all the CSR registers in asm.S 2019-06-25 23:33:40 +03:00
assemble.sh add riscv32i target 2019-07-26 00:13:38 +08:00
build.rs Implement asm functions 2019-01-23 01:29:54 +03:00
check-blobs.sh Implement asm functions 2019-01-23 01:29:54 +03:00

README.md

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riscv

Low level access to RISC-V processors

This project is developed and maintained by the RISC-V team.

Documentation

License

Copyright 2019 RISC-V team

Permission to use, copy, modify, and/or distribute this software for any purpose with or without fee is hereby granted, provided that the above copyright notice and this permission notice appear in all copies.

THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.

Code of Conduct

Contribution to this crate is organized under the terms of the Rust Code of Conduct, the maintainer of this crate, the RISC-V team, promises to intervene to uphold that code of conduct.