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artiq-zynq/src/gateware
morgan cb1ec7f62a CXP upconn: remove unused code 2024-06-17 14:46:49 +08:00
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acpki.py acpki: working 2020-09-09 21:24:49 +08:00
analyzer.py analyzer: report AXI bus errors 2020-07-20 19:51:22 +08:00
config.py refactor `write_rustc_cfg_file()` 2023-09-11 11:48:19 +08:00
cxp.py cxp: refactor to its separte module 2024-06-14 17:17:56 +08:00
cxp_4r_fmc.py cxp fmc: rename file 2024-06-14 17:16:51 +08:00
cxp_downconn.py cxp gtx: rename to cxp_downconn 2024-06-14 17:17:16 +08:00
cxp_upconn.py CXP upconn: remove unused code 2024-06-17 14:46:49 +08:00
ddmtd.py DDMTD: replace 1st edge to median edge deglitcher 2024-04-29 13:05:02 +08:00
dma.py dma: report AXI bus error 2020-07-21 12:47:20 +08:00
drtio_aux_controller.py drtio_aux_controller: support aux_buffer_count 2024-04-24 17:12:39 +08:00
endianness.py dma: fix endianness issues 2020-07-16 17:27:08 +08:00
kasli_soc.py kasli soc: refactor to use wrpll from artiq 2024-05-30 15:25:33 +08:00
test_dma.py RTIO/SYS Clock merge 2023-02-17 15:52:43 +08:00
zc706.py zc706: use new CXP file name 2024-06-14 17:18:26 +08:00
zynq_clocking.py zynq_clocking: Allow ext signal to set cur_clk csr 2023-11-07 18:55:08 +08:00