artiq-zynq

morgan

Author	SHA1	Message	Date
morgan	465609b3f3	cxp coredevice driver: init	2024-10-31 13:16:08 +08:00
morgan	b2ca89149c	api: add cxp api support for CTRL packet	2024-10-31 13:16:08 +08:00
morgan	61b263c630	libboard_artiq: setup libboard_artiq: add cxp_downconn & cxp_upconn libboard_artiq: compile mem with cxp libboard_artiq: add cxp_proto libboard_artiq: add cxp_phys	2024-10-31 13:16:08 +08:00
morgan	1fb5568044	cxp downconn firmware: packet testing	2024-10-31 13:16:08 +08:00
morgan	3cefebd6e5	cxp upconn firmware: packet testing	2024-10-31 13:16:08 +08:00
morgan	762d0c3ca6	cxp protocol: init testing: add packet printing helper function testing: add rx loopback proto FW: use memory buffer for tx and rx proto FW: use byteoder crate to handle endianness proto FW: add event packet reader and writer proto FW: add error correction for 4x char	2024-10-31 13:16:08 +08:00
morgan	d444ae12b4	Cargo: add byteorder	2024-10-31 13:16:08 +08:00
morgan	3af0c222c9	main: add testing	2024-10-31 13:16:08 +08:00
morgan	9a4aa5a717	cxp_phys: low speed serial & GTX setup downconn: add QPLL & GTX setup downconn: add DRP to change linerate up to 12.5Gbps downconn testing: add txuserclk config upconn: add low speed serital setup upconn & downconn: add linerate changer	2024-10-31 13:16:08 +08:00
morgan	ab9fb82a8d	zc706: add CXP_DEMO variant zc706: add fmc pads zc706: add constraint to fix comma alignment & setup/hold time issue zc706: add csr & mem group for cxp zc706: add CXP to rtio_channel	2024-10-31 13:16:08 +08:00
morgan	8ee930084f	cxp: add PHY and pipeline testing: add loopback tx for rx testing testing: add trigger, trigger ack for testing cxp: add upconn & downconn phy cxp: add upconn & downconn pipeline cxp: add rtlink	2024-10-31 13:16:08 +08:00
morgan	b186891f37	cxp pipeline: packet handling pipeline tx pipeline: add CRC32 inserter tx pipeline: add start & end of packet code inserter tx pipeline: add packet wrapper for start & stop packet indication tx pipeline: add code source for trigger & trigger ack packet tx pipeline: add packet for trigger & trigger ack tx pipeline: add test packet generator tx pipeline: add tx_command_packet for firmware tx command packet: add dma to store control packet rx pipeline: add reciever path rx pipeline: add duplicate char decoder rx pipeline: add trig ack checker rx pipeline: add packet decoder decoder: add test packet checher decoder: add packet DMA	2024-10-31 13:16:08 +08:00
morgan	59926aad7c	cxp upconn gw: add low speed serial PHY testing: add debug fifo output b4 encoder cxp upconn: add low speed serial cxp upconn: add reset, tx_busy, tx_enable cxp upconn: add clockgen module for 20.83Mbps & 41.66Mbps using counters cxp upconn: add oserdes using CEInserter	2024-10-31 13:16:08 +08:00
morgan	21492b46e8	cxp downconn gw: add gtx up to 12.5Gbps testing: add txusrclk mmcm & loopback mode testing: add debug output testing: send comma in the middle of long packet to maintain lock downconn: don't put IDLE into fifo downconn: add GTX and QPLL support downconn: add DRP for GTX and QPLL to support all CXP linerates GTX: add gtx with mmcm for TXUSRCLK freq requirement GTX: add loopback mode parameter for testing GTX: add gtx with 40bits internal width GTX: use built-in comma aligner GTX: add comma checker to ensure comma is aligner on highest linerate GTX: set QPLL as CLK source for GTX	2024-10-31 13:16:08 +08:00

1 changed files with 1 additions and 1 deletions

									
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src/gateware/cxp_downconn.py

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				@ -83,7 +83,7 @@ class Receiver(Module):

				            cdc_fifo.source.connect(tx_fifo.sink),

				        ]

				        idle_period = 50 # press in word

				        idle_period = 50 # express in word

				        word_count = Signal(max=idle_period)

				        # JANK: fix the every 98th word got eaten

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src/gateware/cxp_downconn.py

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14 Commits

ef5b06b187 ... 465609b3f3

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src/gateware/cxp_downconn.py

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