forked from M-Labs/artiq-zynq
cxp pipeline: packet handling pipeline
tx pipeline: add CRC32 inserter tx pipeline: add start & end of packet code inserter tx pipeline: add packet wrapper for start & stop packet indication tx pipeline: add code source for trigger & trigger ack packet tx pipeline: add packet for trigger & trigger ack tx pipeline: add test packet generator tx pipeline: add tx_command_packet for firmware tx command packet: add dma to store control packet rx pipeline: add reciever path rx pipeline: add duplicate char decoder rx pipeline: add trig ack checker rx pipeline: add packet decoder decoder: add test packet checher decoder: add packet DMA
This commit is contained in:
parent
59926aad7c
commit
b186891f37
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from migen import *
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from migen.genlib.cdc import MultiReg
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from misoc.interconnect.csr import *
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from misoc.interconnect import stream
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from misoc.cores.liteeth_mini.mac.crc import LiteEthMACCRCEngine, LiteEthMACCRCChecker
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from functools import reduce
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from itertools import combinations
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from operator import or_, and_
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char_width = 8
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char_layout = [("data", char_width), ("k", char_width//8)]
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word_dw = 32
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word_layout = [("data", word_dw), ("k", word_dw//8)]
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word_layout_dchar = [
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("data", word_dw),
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("k", word_dw//8),
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("dchar", char_width),
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("dchar_k", char_width//8)
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]
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buffer_count = 4
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buffer_depth = 512
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def K(x, y):
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return ((y << 5) | x)
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KCode = {
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"pak_start" : C(K(27, 7), char_width),
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"io_ack" : C(K(28, 6), char_width),
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"trig_indic_28_2" : C(K(28, 2), char_width),
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"trig_indic_28_4" : C(K(28, 4), char_width),
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"pak_end" : C(K(29, 7), char_width),
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"idle_comma" : C(K(28, 5), char_width),
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"idle_alignment" : C(K(28, 1), char_width),
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}
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class Packet_Wrapper(Module):
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def __init__(self):
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self.sink = stream.Endpoint(word_layout)
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self.source = stream.Endpoint(word_layout)
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# # #
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self.submodules.fsm = fsm = FSM(reset_state="IDLE")
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fsm.act("IDLE",
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self.sink.ack.eq(1),
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If(self.sink.stb,
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self.sink.ack.eq(0),
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NextState("INSERT_HEADER"),
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)
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)
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fsm.act("INSERT_HEADER",
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self.sink.ack.eq(0),
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self.source.stb.eq(1),
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self.source.data.eq(Replicate(KCode["pak_start"], 4)),
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self.source.k.eq(Replicate(1, 4)),
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If(self.source.ack, NextState("COPY")),
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)
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fsm.act("COPY",
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self.sink.connect(self.source),
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self.source.eop.eq(0),
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If(self.sink.stb & self.sink.eop & self.source.ack,
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NextState("INSERT_FOOTER"),
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),
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)
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fsm.act("INSERT_FOOTER",
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self.sink.ack.eq(0),
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self.source.stb.eq(1),
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self.source.data.eq(Replicate(KCode["pak_end"], 4)),
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self.source.k.eq(Replicate(1, 4)),
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self.source.eop.eq(1),
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If(self.source.ack, NextState("IDLE")),
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)
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class TX_Trigger(Module):
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def __init__(self):
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self.stb = Signal()
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self.delay = Signal(char_width)
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self.linktrig_mode = Signal()
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# # #
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self.sink = stream.Endpoint(char_layout)
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self.source = stream.Endpoint(char_layout)
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# Table 15 & 16 (CXP-001-2021)
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# Send [K28.2, K28.4, K28.4] or [K28.4, K28.2, K28.2] and 3x delay as trigger packet
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trig_packet = [Signal(char_width), Signal(char_width), Signal(char_width), self.delay, self.delay, self.delay]
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trig_packet_k = [1, 1, 1, 0, 0, 0]
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self.comb += [
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If(self.linktrig_mode,
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trig_packet[0].eq(KCode["trig_indic_28_4"]),
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trig_packet[1].eq(KCode["trig_indic_28_2"]),
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trig_packet[2].eq(KCode["trig_indic_28_2"]),
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).Else(
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trig_packet[0].eq(KCode["trig_indic_28_2"]),
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trig_packet[1].eq(KCode["trig_indic_28_4"]),
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trig_packet[2].eq(KCode["trig_indic_28_4"]),
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),
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]
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self.submodules.fsm = fsm = FSM(reset_state="COPY")
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cnt = Signal(max=6)
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fsm.act("COPY",
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NextValue(cnt, cnt.reset),
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self.sink.connect(self.source),
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If(self.stb, NextState("WRITE_TRIG"))
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)
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fsm.act("WRITE_TRIG",
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self.sink.ack.eq(0),
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self.source.stb.eq(1),
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self.source.data.eq(Array(trig_packet)[cnt]),
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self.source.k.eq(Array(trig_packet_k)[cnt]),
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If(self.source.ack,
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If(cnt == 5,
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NextState("COPY"),
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).Else(
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NextValue(cnt, cnt + 1),
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)
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)
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)
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class Idle_Word_Inserter(Module):
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def __init__(self):
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self.stb = Signal()
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# # #
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# Section 9.2.5 (CXP-001-2021)
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# Send K28.5, K28.1, K28.1, D21.5 as idle word
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self.submodules.fsm = fsm = FSM(reset_state="COPY")
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self.sink = stream.Endpoint(word_layout)
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self.source = stream.Endpoint(word_layout)
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fsm.act("COPY",
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self.sink.connect(self.source),
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If(self.stb, NextState("WRITE_IDLE"))
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)
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fsm.act("WRITE_IDLE",
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self.sink.ack.eq(0),
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self.source.stb.eq(1),
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self.source.data.eq(Cat(KCode["idle_comma"], KCode["idle_alignment"], KCode["idle_alignment"], C(0xB5, char_width))),
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self.source.k.eq(Cat(1, 1, 1, 0)),
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If(self.source.ack, NextState("COPY")),
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)
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class Trigger_ACK_Inserter(Module):
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def __init__(self):
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self.stb = Signal()
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# # #
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# Section 9.3.2 (CXP-001-2021)
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# Send 4x K28.6 and 4x 0x01 as trigger packet ack
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self.submodules.fsm = fsm = FSM(reset_state="COPY")
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self.sink = stream.Endpoint(word_layout)
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self.source = stream.Endpoint(word_layout)
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fsm.act("COPY",
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self.sink.connect(self.source),
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If(self.stb, NextState("WRITE_ACK0"))
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)
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fsm.act("WRITE_ACK0",
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self.sink.ack.eq(0),
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self.source.stb.eq(1),
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self.source.data.eq(Replicate(KCode["io_ack"], 4)),
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self.source.k.eq(Replicate(1, 4)),
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If(self.source.ack, NextState("WRITE_ACK1")),
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)
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fsm.act("WRITE_ACK1",
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self.sink.ack.eq(0),
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self.source.stb.eq(1),
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self.source.data.eq(Replicate(C(0x01, char_width), 4)),
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self.source.k.eq(Replicate(0, 4)),
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If(self.source.ack, NextState("COPY")),
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)
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@FullMemoryWE()
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class TX_Bootstrap(Module, AutoCSR):
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def __init__(self):
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self.tx_word_len = CSRStorage(log2_int(buffer_depth))
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self.tx = CSR()
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self.tx_testseq = CSR()
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self.tx_busy = CSRStatus()
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# # #
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self.specials.mem = mem = Memory(word_dw, buffer_depth)
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self.specials.mem_port = mem_port = mem.get_port()
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self.source = stream.Endpoint(word_layout)
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# increment addr in the same cycle the moment addr_inc is high
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# as memory takes one cycle to shift to the correct addr
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addr_next = Signal(log2_int(buffer_depth))
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addr = Signal.like(addr_next)
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addr_rst = Signal()
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addr_inc = Signal()
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self.sync += addr.eq(addr_next),
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self.comb += [
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addr_next.eq(addr),
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If(addr_rst,
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addr_next.eq(addr_next.reset),
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).Elif(addr_inc,
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addr_next.eq(addr + 1),
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),
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mem_port.adr.eq(addr_next),
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self.source.data.eq(mem_port.dat_r)
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]
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self.submodules.fsm = fsm = FSM(reset_state="IDLE")
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self.sync += self.tx_busy.status.eq(~fsm.ongoing("IDLE"))
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cnt = Signal(max=0xFFF)
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fsm.act("IDLE",
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addr_rst.eq(1),
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If(self.tx.re, NextState("TRANSMIT")),
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If(self.tx_testseq.re,
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NextValue(cnt, cnt.reset),
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NextState("WRITE_TEST_PACKET_TYPE"),
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)
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)
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fsm.act("TRANSMIT",
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self.source.stb.eq(1),
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If(self.source.ack,
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addr_inc.eq(1),
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),
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If(addr_next == self.tx_word_len.storage,
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self.source.eop.eq(1),
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NextState("IDLE")
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)
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)
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fsm.act("WRITE_TEST_PACKET_TYPE",
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self.source.stb.eq(1),
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self.source.data.eq(Replicate(C(0x04, char_width), 4)),
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self.source.k.eq(Replicate(0, 4)),
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If(self.source.ack,NextState("WRITE_TEST_COUNTER"))
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)
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fsm.act("WRITE_TEST_COUNTER",
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self.source.stb.eq(1),
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self.source.data.eq(Cat(cnt[:8], cnt[:8]+1, cnt[:8]+2, cnt[:8]+3)),
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self.source.k.eq(Cat(0, 0, 0, 0)),
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If(self.source.ack,
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If(cnt == 0xFFF-3,
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self.source.eop.eq(1),
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NextState("IDLE")
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).Else(
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NextValue(cnt, cnt + 4),
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)
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)
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)
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class RX_Debug_Buffer(Module,AutoCSR):
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def __init__(self):
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self.submodules.buf_out = buf_out = stream.SyncFIFO(word_layout_dchar, 128)
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self.sink = buf_out.sink
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self.inc = CSR()
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self.dout_pak = CSRStatus(word_dw)
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self.kout_pak = CSRStatus(word_dw//8)
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self.dout_valid = CSRStatus()
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self.sync += [
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# output
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buf_out.source.ack.eq(self.inc.re),
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self.dout_pak.status.eq(buf_out.source.data),
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self.kout_pak.status.eq(buf_out.source.k),
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self.dout_valid.status.eq(buf_out.source.stb),
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]
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class Duplicated_Char_Decoder(Module):
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def __init__(self):
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self.sink = stream.Endpoint(word_layout)
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self.buffer = stream.Endpoint(word_layout)
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self.source = stream.Endpoint(word_layout_dchar)
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# # #
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# For duplicated characters, an error correction method (e.g. majority voting) is required to meet the CXP spec:
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# RX decoder should immune to single bit errors when handling duplicated characters - Section 9.2.2.1 (CXP-001-2021)
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#
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#
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# 32
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# +---> buffer -----/-----+
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# 32 | | 32+8(dchar)
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# sink ---/---+ ---> source -----/-----> downstream
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# | 8(dchar) | decoders
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# +---> majority -----/-----+
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# voting
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#
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#
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# Due to the tight setup/hold time requiremnt for 12.5Gbps CXP, the voting logic cannot be implemented as combinational logic
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# Hence, a pipeline approach is needed to avoid any s/h violation, where the majority voting result are pre-calculate and injected into the bus immediate after the PHY.
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# And any downstream modules can access the voting result without implementing the voting logic inside the decoder
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self.sync += [
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self.sink.ack.eq(self.buffer.ack),
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self.buffer.stb.eq(self.sink.stb),
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If(self.sink.stb,
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self.buffer.data.eq(self.sink.data),
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self.buffer.k.eq(self.sink.k),
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),
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]
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# cycle 1 - calculate ABC, ABD, ACD & BCD
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char = [[self.sink.data[i*8:(i+1)*8], self.sink.k[i]] for i in range(4)]
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voters = [Record([("data", 8), ("k", 1)]) for _ in range(4)]
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for i, comb in enumerate(combinations(char, 3)):
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self.sync += [
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If(self.sink.stb,
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voters[i].data.eq(reduce(and_, [code[0] for code in comb])),
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voters[i].k.eq(reduce(and_, [code[1] for code in comb])),
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)
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]
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# cycle 2 - inject the voting result
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self.sync += [
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self.buffer.ack.eq(self.source.ack),
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self.source.stb.eq(self.buffer.stb),
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If(self.buffer.stb,
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self.source.data.eq(self.buffer.data),
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self.source.k.eq(self.buffer.k),
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self.source.dchar.eq(Replicate(reduce(or_, [v.data for v in voters]), 4)),
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self.source.dchar_k.eq(Replicate(reduce(or_, [v.k for v in voters]), 4)),
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),
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]
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@FullMemoryWE()
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class RX_Bootstrap(Module):
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def __init__(self):
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self.packet_type = Signal(8)
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self.decode_err = Signal()
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self.test_err = Signal()
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self.buffer_err = Signal()
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# # #
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# TODO: heartbeat
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type = {
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"data_stream": 0x01,
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"control_ack_no_tag": 0x03,
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"test_packet": 0x04,
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"control_ack_with_tag": 0x06,
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"event": 0x07,
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"heartbeat": 0x09,
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}
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self.sink = stream.Endpoint(word_layout_dchar)
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self.source = stream.Endpoint(word_layout_dchar)
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self.submodules.fsm = fsm = FSM(reset_state="IDLE")
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fsm.act("IDLE",
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self.sink.ack.eq(1),
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If((self.sink.stb & (self.sink.dchar == KCode["pak_start"]) & (self.sink.dchar_k == 1)),
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NextState("DECODE"),
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)
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)
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cnt = Signal(max=0x100)
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addr_nbits = log2_int(buffer_depth)
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addr = Signal(addr_nbits)
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fsm.act("DECODE",
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self.sink.ack.eq(1),
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If(self.sink.stb,
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NextValue(self.packet_type, self.sink.dchar),
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Case(self.sink.dchar, {
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type["data_stream"]: NextState("STREAMING"),
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type["test_packet"]: [
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NextValue(cnt, cnt.reset),
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NextState("VERIFY_TEST_PATTERN"),
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],
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type["control_ack_no_tag"]:[
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NextValue(addr, addr.reset),
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NextState("LOAD_BUFFER"),
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],
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type["control_ack_with_tag"]:[
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NextValue(addr, addr.reset),
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NextState("LOAD_BUFFER"),
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],
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type["event"]: [
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NextValue(addr, addr.reset),
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NextState("LOAD_BUFFER"),
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],
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"default": [
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self.decode_err.eq(1),
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# wait till next valid packet
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NextState("IDLE"),
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],
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}),
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)
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)
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# For stream data packet
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fsm.act("STREAMING",
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If((self.sink.stb & (self.sink.dchar == KCode["pak_end"]) & (self.sink.dchar_k == 1)),
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# discard K29,7
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self.sink.ack.eq(1),
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NextState("IDLE")
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).Else(
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self.sink.connect(self.source),
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)
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)
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# Section 9.9.1 (CXP-001-2021)
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# the received test data packet (0x00, 0x01 ... 0xFF)
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# need to be compared against the local test sequence generator
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fsm.act("VERIFY_TEST_PATTERN",
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self.sink.ack.eq(1),
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If(self.sink.stb,
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If(((self.sink.dchar == KCode["pak_end"]) & (self.sink.dchar_k == 1)),
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NextState("IDLE"),
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).Else(
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If(((self.sink.data != Cat(cnt, cnt+1, cnt+2, cnt+3))),
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self.test_err.eq(1),
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),
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If(cnt == 0xFC,
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NextValue(cnt, cnt.reset),
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).Else(
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NextValue(cnt, cnt + 4)
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)
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)
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)
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)
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|
||||
# A circular buffer for firmware to read packet from
|
||||
self.specials.mem = mem = Memory(word_dw, buffer_count*buffer_depth)
|
||||
self.specials.mem_port = mem_port = mem.get_port(write_capable=True)
|
||||
|
||||
write_ptr = Signal(log2_int(buffer_count))
|
||||
self.write_ptr_sys = Signal.like(write_ptr)
|
||||
self.specials += MultiReg(write_ptr, self.write_ptr_sys),
|
||||
|
||||
self.comb += [
|
||||
mem_port.adr[:addr_nbits].eq(addr),
|
||||
mem_port.adr[addr_nbits:].eq(write_ptr),
|
||||
]
|
||||
|
||||
# For control ack, event packet
|
||||
fsm.act("LOAD_BUFFER",
|
||||
mem_port.we.eq(0),
|
||||
self.sink.ack.eq(1),
|
||||
If(self.sink.stb,
|
||||
If(((self.sink.dchar == KCode["pak_end"]) & (self.sink.dchar_k == 1)),
|
||||
NextState("MOVE_BUFFER_PTR"),
|
||||
).Else(
|
||||
mem_port.we.eq(1),
|
||||
mem_port.dat_w.eq(self.sink.data),
|
||||
NextValue(addr, addr + 1),
|
||||
If(addr == buffer_depth - 1,
|
||||
# discard the packet
|
||||
self.buffer_err.eq(1),
|
||||
NextState("IDLE"),
|
||||
)
|
||||
)
|
||||
)
|
||||
)
|
||||
|
||||
self.read_ptr_rx = Signal.like(write_ptr)
|
||||
fsm.act("MOVE_BUFFER_PTR",
|
||||
self.sink.ack.eq(0),
|
||||
If(write_ptr + 1 == self.read_ptr_rx,
|
||||
# if next one hasn't been read, overwrite the current buffer when new packet comes in
|
||||
self.buffer_err.eq(1),
|
||||
).Else(
|
||||
NextValue(write_ptr, write_ptr + 1),
|
||||
),
|
||||
NextState("IDLE"),
|
||||
)
|
||||
|
||||
class Trigger_Ack_Checker(Module, AutoCSR):
|
||||
def __init__(self):
|
||||
self.sink = stream.Endpoint(word_layout_dchar)
|
||||
self.source = stream.Endpoint(word_layout_dchar)
|
||||
|
||||
self.ack = Signal()
|
||||
|
||||
# # #
|
||||
|
||||
self.submodules.fsm = fsm = FSM(reset_state="COPY")
|
||||
|
||||
fsm.act("COPY",
|
||||
If((self.sink.stb & (self.sink.dchar == KCode["io_ack"]) & (self.sink.dchar_k == 1)),
|
||||
# discard K28,6
|
||||
self.sink.ack.eq(1),
|
||||
NextState("CHECK_ACK")
|
||||
).Else(
|
||||
self.sink.connect(self.source),
|
||||
)
|
||||
)
|
||||
|
||||
fsm.act("CHECK_ACK",
|
||||
If(self.sink.stb,
|
||||
NextState("COPY"),
|
||||
# discard the word after K28,6
|
||||
self.sink.ack.eq(1),
|
||||
If((self.sink.dchar == 0x01) & (self.sink.dchar_k == 0),
|
||||
self.ack.eq(1),
|
||||
)
|
||||
)
|
||||
)
|
||||
|
||||
@ResetInserter()
|
||||
@CEInserter()
|
||||
class CXPCRC32(Module):
|
||||
# Section 9.2.2.2 (CXP-001-2021)
|
||||
width = 32
|
||||
polynom = 0x04C11DB7
|
||||
seed = 2**width-1
|
||||
check = 0x00000000
|
||||
def __init__(self, data_width):
|
||||
self.data = Signal(data_width)
|
||||
self.value = Signal(self.width)
|
||||
self.error = Signal()
|
||||
|
||||
# # #
|
||||
|
||||
self.submodules.engine = LiteEthMACCRCEngine(data_width, self.width, self.polynom)
|
||||
reg = Signal(self.width, reset=self.seed)
|
||||
self.sync += reg.eq(self.engine.next)
|
||||
self.comb += [
|
||||
self.engine.data.eq(self.data),
|
||||
self.engine.last.eq(reg),
|
||||
|
||||
self.value.eq(reg[::-1]),
|
||||
self.error.eq(self.engine.next != self.check)
|
||||
]
|
||||
|
||||
# For verifying crc in stream data packet
|
||||
class CXPCRC32Checker(LiteEthMACCRCChecker):
|
||||
def __init__(self, layout):
|
||||
LiteEthMACCRCChecker.__init__(self, CXPCRC32, layout)
|
||||
Loading…
Reference in New Issue