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b4a75fd8c9
...
465609b3f3
393
sim_pipeline.py
393
sim_pipeline.py
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@ -1,393 +0,0 @@
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from migen import *
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from misoc.interconnect.csr import *
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from misoc.interconnect import stream
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from misoc.cores.liteeth_mini.mac.crc import LiteEthMACCRCEngine
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from src.gateware.cxp_pipeline import *
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class EOP_Marker(Module):
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def __init__(self):
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self.sink = stream.Endpoint(word_layout_dchar)
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self.source = stream.Endpoint(word_layout_dchar)
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# # #
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last_stb = Signal()
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self.sync += [
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If((~self.source.stb | self.source.ack),
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self.source.stb.eq(self.sink.stb),
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self.source.payload.eq(self.sink.payload),
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),
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last_stb.eq(self.sink.stb),
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]
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self.comb += [
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self.sink.ack.eq(~self.source.stb | self.source.ack),
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self.source.eop.eq(~self.sink.stb & last_stb),
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]
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class Stream_MetaData_Extractor(Module):
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def __init__(self):
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self.sink = stream.Endpoint(word_layout_dchar)
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self.source = stream.Endpoint(word_layout_dchar)
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# # #
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# GOAL:
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# 0) accept four sinks??
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# 1) decode SPH, SPT
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# 2) decode Image header, line break
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# 3) verify the crc before phrasing image data downstream
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# HOW??
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# combine streams?
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# phrase linedata to sys CD
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# check stream data tag
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# only need to support mono16 for now
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self.stream_id = Signal(char_width)
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self.pak_tag = Signal(char_width)
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self.stream_pak_size = Signal(char_width * 2)
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self.submodules.fsm = fsm = FSM(reset_state="WAIT_HEADER")
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fsm.act(
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"WAIT_HEADER",
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NextValue(self.stream_id, self.stream_id.reset),
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NextValue(self.pak_tag, self.pak_tag.reset),
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NextValue(self.stream_pak_size, self.stream_pak_size.reset),
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self.sink.ack.eq(1),
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If(
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self.sink.stb,
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NextValue(self.stream_id, self.sink.dchar),
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NextState("GET_PAK_TAG"),
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),
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)
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fsm.act(
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"GET_PAK_TAG",
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If(
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self.sink.stb,
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self.sink.ack.eq(1),
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NextValue(self.pak_tag, self.sink.dchar),
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NextState("GET_PAK_SIZE_0"),
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),
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)
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fsm.act(
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"GET_PAK_SIZE_0",
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self.sink.ack.eq(1),
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If(
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self.sink.stb,
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NextValue(self.stream_pak_size[8:], self.sink.dchar),
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NextState("GET_PAK_SIZE_1"),
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),
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)
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fsm.act(
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"GET_PAK_SIZE_1",
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self.sink.ack.eq(1),
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If(
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self.sink.stb,
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NextValue(self.stream_pak_size[:8], self.sink.dchar),
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NextState("STORE_BUFFER"),
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),
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)
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fsm.act(
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"STORE_BUFFER",
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self.sink.connect(self.source),
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# both serve the same function but using the pak size I can remove eop injecter and save 1 cycle
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If(self.sink.stb,
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NextValue(self.stream_pak_size, self.stream_pak_size - 1),
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If(self.stream_pak_size == 1,
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NextState("WAIT_HEADER"),
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)
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),
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# If((self.sink.stb & self.sink.eop),
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# NextState("WAIT_HEADER"),
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# )
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)
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class Frame_Decoder(Module):
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def __init__(self):
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self.sink = stream.Endpoint(word_layout_dchar)
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self.source = stream.Endpoint(word_layout_dchar)
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# # #
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# TODO: decode Image header, line break
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class Pixel_Decoder(Module):
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def __init__(self, pixel_format="mono16"):
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assert pixel_format == "mono16"
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self.sink = stream.Endpoint(word_layout_dchar)
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self.source = stream.Endpoint(word_layout_dchar)
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# # #
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# TODO: support mono16 for now?
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class Streams_Dispatcher(Module):
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def __init__(self, downconns):
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n_downconn = len(downconns)
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self.submodules.mux = mux = stream.Multiplexer(word_layout_dchar, n_downconn)
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for i, c in enumerate(downconns):
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# if i == 0:
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self.comb += [
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# no backpressure
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c.source.ack.eq(1),
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c.source.connect(getattr(mux, "sink"+str(i)))
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]
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self.source = stream.Endpoint(word_layout_dchar)
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self.submodules.fsm = fsm = FSM(reset_state="WAIT_HEADER")
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# TODO: add different downstream
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# stream_id = Signal()
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# case = dict((i, mux.source.connect(b.sink)) for i, b in enumerate(buffers))
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fsm.act(
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"WAIT_HEADER",
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mux.source.connect(self.source),
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If(mux.source.eop,
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NextState("SWITCH_CONN"),
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),
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)
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read_mask = Signal(max=n_downconn)
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self.comb += mux.sel.eq(read_mask)
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fsm.act(
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"SWITCH_CONN",
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If(read_mask == n_downconn - 1,
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NextValue(read_mask, read_mask.reset),
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).Else(
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NextValue(read_mask, read_mask + 1),
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),
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NextState("WAIT_HEADER"),
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)
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def reverse_bytes(s):
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assert len(s) % 8 == 0
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char = [s[i*8:(i+1)*8] for i in range(len(s)//8)]
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return Cat(char[::-1])
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@ResetInserter()
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@CEInserter()
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class CXPCRC32(Module):
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# Section 9.2.2.2 (CXP-001-2021)
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width = 32
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polynom = 0x04C11DB7
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seed = 2**width - 1
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check = 0x00000000
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def __init__(self, data_width):
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self.data = Signal(data_width)
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self.value = Signal(self.width)
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self.error = Signal()
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# # #
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self.submodules.engine = LiteEthMACCRCEngine(
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data_width, self.width, self.polynom
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)
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reg = Signal(self.width, reset=self.seed)
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self.sync += reg.eq(self.engine.next)
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self.comb += [
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# the CRC Engine use Big Endian, need to reverse the bytes
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self.engine.data.eq(reverse_bytes(self.data)),
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self.engine.last.eq(reg),
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self.value.eq(reverse_bytes(reg[::-1])),
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self.error.eq(reg != self.check),
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]
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class CXPCRC32Inserter(Module):
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def __init__(self):
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self.sink = stream.Endpoint(word_layout)
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self.source = stream.Endpoint(word_layout)
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# # #
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self.submodules.crc = crc = CXPCRC32(word_dw)
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self.submodules.fsm = fsm = FSM(reset_state="IDLE")
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fsm.act("IDLE",
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crc.reset.eq(1),
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self.sink.ack.eq(1),
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If(self.sink.stb,
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self.sink.ack.eq(0),
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NextState("COPY"),
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)
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)
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fsm.act("COPY",
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crc.ce.eq(self.sink.stb & self.source.ack),
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crc.data.eq(self.sink.data),
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self.sink.connect(self.source),
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self.source.eop.eq(0),
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If(self.sink.stb & self.sink.eop & self.source.ack,
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NextState("INSERT"),
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)
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)
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fsm.act("INSERT",
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self.source.stb.eq(1),
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self.source.eop.eq(1),
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self.source.data.eq(crc.value),
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If(self.source.ack, NextState("IDLE"))
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)
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class StreamPacket_Wrapper(Module):
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def __init__(self):
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self.sink = stream.Endpoint(word_layout)
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self.source = stream.Endpoint(word_layout)
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# # #
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self.submodules.fsm = fsm = FSM(reset_state="IDLE")
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fsm.act("IDLE",
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self.sink.ack.eq(1),
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If(self.sink.stb,
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self.sink.ack.eq(0),
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NextState("INSERT_HEADER_0"),
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)
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)
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fsm.act("INSERT_HEADER_0",
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self.sink.ack.eq(0),
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self.source.stb.eq(1),
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self.source.data.eq(Replicate(KCode["pak_start"], 4)),
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self.source.k.eq(Replicate(1, 4)),
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If(self.source.ack, NextState("INSERT_HEADER_1")),
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)
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fsm.act("INSERT_HEADER_1",
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self.sink.ack.eq(0),
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self.source.stb.eq(1),
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self.source.data.eq(Replicate(C(0x01, char_width), 4)),
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self.source.k.eq(Replicate(0, 4)),
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If(self.source.ack, NextState("COPY")),
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)
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fsm.act("COPY",
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self.sink.connect(self.source),
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self.source.eop.eq(0),
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If(self.sink.stb & self.sink.eop & self.source.ack,
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NextState("INSERT_FOOTER"),
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),
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)
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fsm.act("INSERT_FOOTER",
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self.sink.ack.eq(0),
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self.source.stb.eq(1),
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self.source.data.eq(Replicate(KCode["pak_end"], 4)),
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self.source.k.eq(Replicate(1, 4)),
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# Simulate RX don't have eop tagged
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# self.source.eop.eq(1),
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If(self.source.ack, NextState("IDLE")),
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)
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# With KCode & 0x01*4
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class StreamData_Generator(Module):
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def __init__(self):
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# should be big enough for all test
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self.submodules.buffer = buffer = stream.SyncFIFO(word_layout, 32)
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self.submodules.crc_inserter = crc_inserter = CXPCRC32Inserter()
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self.submodules.wrapper = wrapper = StreamPacket_Wrapper()
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# # #
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pipeline = [buffer, crc_inserter, wrapper]
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for s, d in zip(pipeline, pipeline[1:]):
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self.comb += s.source.connect(d.sink)
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self.sink = pipeline[0].sink
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self.source = pipeline[-1].source
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# For verifying crc in stream data packet
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class Double_Stream_Buffer(Module):
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# default size is 2 kBtyes - Section 9.5.2 (CXP-001-2021)
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def __init__(self, size=16000):
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# detect and tag end of packet for crc
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# self.submodules.eop_marker = eop_marker = EOP_Marker()
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# self.sink = eop_marker.sink
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self.sink = stream.Endpoint(word_layout_dchar)
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self.submodules.crc = crc = CXPCRC32(word_dw)
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self.comb += crc.data.eq(self.sink.data)
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self.submodules.fsm = fsm = FSM(reset_state="RESET")
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write_mask = Signal()
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self.submodules.line_buffer0 = line_buffer0 = ResetInserter()(stream.SyncFIFO(word_layout_dchar, 2**bits_for(size//word_dw)))
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self.submodules.line_buffer1 = line_buffer1 = ResetInserter()(stream.SyncFIFO(word_layout_dchar, 2**bits_for(size//word_dw)))
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fsm.act("RESET",
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Case(write_mask,
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{
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0: line_buffer0.reset.eq(1),
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1: line_buffer1.reset.eq(1),
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}
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),
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crc.reset.eq(1),
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NextState("CHECKING"),
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)
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fsm.act("CHECKING",
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self.sink.ack.eq(1),
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If(self.sink.stb,
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crc.ce.eq(1),
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If(self.sink.eop,
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# discard the crc at the end
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NextState("SWITCH_BUFFER")
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).Else(
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If(write_mask == 0,
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self.sink.connect(line_buffer0.sink),
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).Else(
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self.sink.connect(line_buffer1.sink),
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),
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)
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)
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)
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# only valid data will be passed to downstream
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fsm.act("SWITCH_BUFFER",
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If(~crc.error,
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NextValue(write_mask, ~write_mask),
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),
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NextState("RESET"),
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)
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self.submodules.mux = mux = stream.Multiplexer(word_layout_dchar, 2)
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self.comb += [
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line_buffer0.source.connect(mux.sink0),
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line_buffer1.source.connect(mux.sink1),
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mux.sel.eq(~write_mask),
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]
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self.source = mux.source
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# DEBUG:
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self.write = Signal()
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self.error = Signal()
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self.comb += [
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self.write.eq(write_mask),
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self.error.eq(crc.error),
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]
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# # to add eop in the same cycle
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# # the tricks relies on the fact source lags sink one cycle
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# # but fsm .connect by default use combinational logic which the same cycle rising/falling edge check immpossible
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# fsm.act("CHECKING",
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# NextValue(self.source.payload.raw_bits(), 0),
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# NextValue(self.source.stb, 0),
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# If(self.sink.stb,
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# crc.ce.eq(1),
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# If(self.sink.eop,
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# NextState("RESET")
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# ).Else(
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# NextValue(self.source.payload.raw_bits(), self.sink.payload.raw_bits()),
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# NextValue(self.source.stb, 1),
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# )
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# )
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# )
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# last_eop = Signal()
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# self.comb += self.source.eop.eq(~last_eop & self.sink.eop)
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159
sim_stream.py
159
sim_stream.py
|
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@ -1,159 +0,0 @@
|
|||
from migen import *
|
||||
from misoc.interconnect import stream
|
||||
from sim_pipeline import *
|
||||
|
||||
from src.gateware.cxp_pipeline import *
|
||||
|
||||
class CXP_Links(Module):
|
||||
def __init__(self):
|
||||
# TODO: select the correct buffer to read from
|
||||
# NOTE: although there are double buffer in each connect, the reading must be faster than writing to avoid data loss
|
||||
|
||||
self.downconns = []
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for i in range(2):
|
||||
downconn = Pipeline()
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setattr(self.submodules, "cxp_conn"+str(i), downconn)
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self.downconns.append(downconn)
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self.submodules.dispatcher = dispatcher = Streams_Dispatcher(self.downconns)
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|
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# TODO: add extractor
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||||
# self.submodules.double_buffer = double_buffer = Double_Stream_Buffer()
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||||
pipeline = [dispatcher]
|
||||
for s, d in zip(pipeline, pipeline[1:]):
|
||||
self.comb += s.source.connect(d.sink)
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||||
self.source = pipeline[-1].source
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|
||||
# no backpressure
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||||
self.sync += self.source.ack.eq(1)
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|
||||
|
||||
class Pipeline(Module):
|
||||
def __init__(self):
|
||||
self.submodules.generator = generator = StreamData_Generator()
|
||||
self.submodules.dchar_decoder = dchar_decoder = Duplicated_Char_Decoder()
|
||||
self.submodules.data_decoder = data_decoder = RX_Bootstrap()
|
||||
self.submodules.eop_marker = eop_marker = EOP_Marker()
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||||
|
||||
# # #
|
||||
|
||||
pipeline = [generator, dchar_decoder, data_decoder, eop_marker]
|
||||
for s, d in zip(pipeline, pipeline[1:]):
|
||||
self.comb += s.source.connect(d.sink)
|
||||
self.sink = pipeline[0].sink
|
||||
self.source = pipeline[-1].source
|
||||
|
||||
# self.comb += self.source.ack.eq(1)
|
||||
|
||||
|
||||
dut = CXP_Links()
|
||||
|
||||
def check_case(packet=[]):
|
||||
|
||||
|
||||
|
||||
print("=================TEST========================")
|
||||
downconns = dut.downconns
|
||||
ch = 0
|
||||
|
||||
for i, p in enumerate(packet):
|
||||
for x in range(len(downconns)):
|
||||
if x == ch:
|
||||
yield downconns[x].sink.data.eq(p["data"])
|
||||
yield downconns[x].sink.k.eq(p["k"])
|
||||
yield downconns[x].sink.stb.eq(1)
|
||||
else:
|
||||
yield downconns[x].sink.data.eq(0)
|
||||
yield downconns[x].sink.k.eq(0)
|
||||
yield downconns[x].sink.stb.eq(0)
|
||||
yield downconns[x].sink.eop.eq(0)
|
||||
if "eop" in p:
|
||||
yield downconns[ch].sink.eop.eq(1)
|
||||
# compensate for delay
|
||||
# yield
|
||||
# yield downconns[ch].sink.data.eq(0)
|
||||
# yield downconns[ch].sink.k.eq(0)
|
||||
# yield downconns[ch].sink.stb.eq(0)
|
||||
# yield downconns[ch].sink.eop.eq(0)
|
||||
# yield
|
||||
# yield
|
||||
# yield
|
||||
ch = (ch + 1) % len(downconns)
|
||||
else:
|
||||
yield downconns[ch].sink.eop.eq(0)
|
||||
|
||||
# check cycle result
|
||||
yield
|
||||
source = dut.dispatcher.mux.source
|
||||
print(
|
||||
f"\nCYCLE#{i} : source char = {yield source.data:#X} k = {yield source.k:#X} stb = {yield source.stb} ack = {yield source.ack} eop = {yield source.eop}"
|
||||
# f" source dchar = {yield source.dchar:#X} dchar_k = {yield source.dchar_k:#X}"
|
||||
f"\nCYCLE#{i} : read mask = {yield dut.dispatcher.mux.sel}"
|
||||
# f"\nCYCLE#{i} : stream id = {yield decoder.stream_id:#X} pak_tag = {yield decoder.pak_tag:#X}"
|
||||
# f" stream_pak_size = {yield decoder.stream_pak_size:#X}"
|
||||
)
|
||||
# crc = downconns[1].generator.crc_inserter.crc
|
||||
# crc = dut.double_buffer.crc
|
||||
# print(
|
||||
# f"CYCLE#{i} : crc error = {yield crc.error:#X} crc value = {yield crc.value:#X}"
|
||||
# f" crc data = {yield crc.data:#X} engine next = {yield crc.engine.next:#X} ce = {yield crc.ce}"
|
||||
# )
|
||||
|
||||
|
||||
# extra clk cycles
|
||||
cyc = i + 1
|
||||
for i in range(cyc, cyc + 30):
|
||||
for x in range(len(downconns)):
|
||||
# yield won't reset every cycle
|
||||
yield downconns[x].sink.data.eq(0)
|
||||
yield downconns[x].sink.k.eq(0)
|
||||
yield downconns[x].sink.stb.eq(0)
|
||||
yield downconns[x].sink.eop.eq(0)
|
||||
yield
|
||||
print(
|
||||
f"\nCYCLE#{i} : source char = {yield source.data:#X} k = {yield source.k:#X} stb = {yield source.stb} ack = {yield source.ack} eop = {yield source.eop}"
|
||||
# f" source dchar = {yield source.dchar:#X} dchar_k = {yield source.dchar_k:#X}"
|
||||
f"\nCYCLE#{i} : read mask = {yield dut.dispatcher.mux.sel}"
|
||||
# f"\nCYCLE#{i} : stream id = {yield decoder.stream_id:#X} pak_tag = {yield decoder.pak_tag:#X}"
|
||||
# f" stream_pak_size = {yield decoder.stream_pak_size:#X}"
|
||||
)
|
||||
assert True
|
||||
|
||||
|
||||
def testbench():
|
||||
stream_id = 0x69
|
||||
streams = [
|
||||
[
|
||||
{"data": 0x11111111, "k": Replicate(0, 4)},
|
||||
{"data": 0xB105F00D, "k": Replicate(0, 4)},
|
||||
],
|
||||
[
|
||||
{"data": 0x22222222, "k": Replicate(0, 4)},
|
||||
{"data": 0xC00010FF, "k": Replicate(0, 4)},
|
||||
],
|
||||
[
|
||||
{"data": 0x33333333, "k": Replicate(0, 4)},
|
||||
{"data": 0xC0A79AE5, "k": Replicate(0, 4)},
|
||||
],
|
||||
]
|
||||
|
||||
packet = []
|
||||
for i, s in enumerate(streams):
|
||||
s[-1]["eop"] = 0
|
||||
packet += [
|
||||
{"data": Replicate(C(stream_id, char_width), 4), "k": Replicate(0, 4)},
|
||||
{"data": Replicate(C(i, char_width), 4), "k": Replicate(0, 4)},
|
||||
{
|
||||
"data": Replicate(C(len(s) >> 8 & 0xFF, char_width), 4),
|
||||
"k": Replicate(0, 4),
|
||||
},
|
||||
{"data": Replicate(C(len(s) & 0xFF, char_width), 4), "k": Replicate(0, 4)},
|
||||
*s,
|
||||
]
|
||||
|
||||
|
||||
yield from check_case(packet)
|
||||
|
||||
|
||||
run_simulation(dut, testbench(), vcd_name="sim-cxp.vcd")
|
||||
|
|
@ -58,7 +58,7 @@ class Receiver(Module):
|
|||
|
||||
data_valid = Signal()
|
||||
self.sync.cxp_gtx_rx += [
|
||||
data_valid.eq(gtx.comma_aligner.rxfsm.ongoing("READY")),
|
||||
data_valid.eq(gtx.comma_checker.rxfsm.ongoing("READY")),
|
||||
|
||||
self.source.stb.eq(0),
|
||||
If(data_valid & self.source.ack & ~((gtx.decoders[0].d == 0xBC) & (gtx.decoders[0].k == 1)),
|
||||
|
|
@ -218,33 +218,9 @@ class QPLL(Module, AutoCSR):
|
|||
),
|
||||
]
|
||||
|
||||
|
||||
class RX_Resetter(Module):
|
||||
def __init__(self, reset_period=10_000_000):
|
||||
self.rx_ready = Signal()
|
||||
self.rx_reset = Signal()
|
||||
|
||||
# # #
|
||||
|
||||
# periodically reset rx until rx is connected and receiving valid data
|
||||
# as after connecting RXP/RXN, the whole RX need to be reset
|
||||
|
||||
reset_counter = Signal(reset=reset_period-1, max=reset_period)
|
||||
self.sync += [
|
||||
self.rx_reset.eq(0),
|
||||
If(~self.rx_ready,
|
||||
If(reset_counter == 0,
|
||||
reset_counter.eq(reset_counter.reset),
|
||||
self.rx_reset.eq(1),
|
||||
).Else(
|
||||
reset_counter.eq(reset_counter - 1),
|
||||
)
|
||||
)
|
||||
]
|
||||
|
||||
# Warning: Xilinx transceivers are LSB first, and comma needs to be flipped
|
||||
# compared to the usual 8b10b binary representation.
|
||||
class Comma_Aligner(Module):
|
||||
class Comma_Checker(Module):
|
||||
def __init__(self, comma, reset_period=10_000_000):
|
||||
self.data = Signal(20)
|
||||
self.comma_aligned = Signal()
|
||||
|
|
@ -253,9 +229,28 @@ class Comma_Aligner(Module):
|
|||
|
||||
self.aligner_en = Signal()
|
||||
self.ready_sys = Signal()
|
||||
self.restart_sys = Signal()
|
||||
|
||||
# # #
|
||||
|
||||
|
||||
# periodically reset rx until rx is connected and receiving valid data
|
||||
# as after connecting RXP/RXN, the whole RX need to be reset
|
||||
|
||||
reset_counter = Signal(reset=reset_period-1, max=reset_period)
|
||||
self.sync += [
|
||||
self.restart_sys.eq(0),
|
||||
If(~self.ready_sys,
|
||||
If(reset_counter == 0,
|
||||
reset_counter.eq(reset_counter.reset),
|
||||
self.restart_sys.eq(1),
|
||||
).Else(
|
||||
reset_counter.eq(reset_counter - 1),
|
||||
)
|
||||
)
|
||||
]
|
||||
|
||||
|
||||
# Data and comma checker
|
||||
# From UG476 (v1.12.1) p.228
|
||||
# The built-in RXBYTEISALIGNED can be falsely asserted at linerate higher than 5Gbps
|
||||
|
|
@ -699,29 +694,14 @@ class GTX(Module):
|
|||
Instance("BUFG", i_I=txpll_clkout, o_O=self.cd_cxp_gtx_tx.clk),
|
||||
AsyncResetSynchronizer(self.cd_cxp_gtx_tx, ~self.txpll_locked & ~tx_init.done)
|
||||
]
|
||||
self.comb += tx_init.restart.eq(self.tx_restart)
|
||||
|
||||
# RX clocking
|
||||
# the CDR matches the required frequency for RXUSRCLK, no need for PLL
|
||||
|
||||
# Slave Rx will use cxp_gtx_rx instead
|
||||
if rx_mode == "single" or rx_mode == "master":
|
||||
self.clock_domains.cd_cxp_gtx_rx = ClockDomain()
|
||||
self.specials += [
|
||||
Instance("BUFG", i_I=self.rxoutclk, o_O=self.cd_cxp_gtx_rx.clk),
|
||||
AsyncResetSynchronizer(self.cd_cxp_gtx_rx, ~rx_init.done)
|
||||
]
|
||||
self.submodules.rx_resetter = rx_resetter = RX_Resetter()
|
||||
self.comb += [
|
||||
rx_resetter.rx_ready.eq(self.rx_ready),
|
||||
rx_init.restart.eq(self.rx_restart | rx_resetter.rx_reset),
|
||||
]
|
||||
else:
|
||||
self.comb += rx_init.restart.eq(self.rx_restart),
|
||||
|
||||
|
||||
|
||||
# 8b10b Encoder/Decoder
|
||||
self.clock_domains.cd_cxp_gtx_rx = ClockDomain()
|
||||
self.specials += [
|
||||
Instance("BUFG", i_I=self.rxoutclk, o_O=self.cd_cxp_gtx_rx.clk),
|
||||
AsyncResetSynchronizer(self.cd_cxp_gtx_rx, ~rx_init.done)
|
||||
]
|
||||
|
||||
self.comb += [
|
||||
txdata.eq(Cat(self.encoder.output[0], self.encoder.output[1], self.encoder.output[2], self.encoder.output[3])),
|
||||
|
|
@ -731,12 +711,16 @@ class GTX(Module):
|
|||
self.decoders[3].input.eq(rxdata[30:]),
|
||||
]
|
||||
|
||||
self.submodules.comma_aligner = comma_aligner = Comma_Aligner(0b0101111100)
|
||||
|
||||
self.submodules.comma_checker = comma_checker = Comma_Checker(0b0101111100)
|
||||
self.comb += [
|
||||
comma_aligner.data.eq(rxdata),
|
||||
comma_aligner.comma_aligned.eq(comma_aligned),
|
||||
comma_aligner.comma_realigned.eq(comma_realigned),
|
||||
comma_aligner.comma_det.eq(comma_det),
|
||||
comma_aligner_en.eq(comma_aligner.aligner_en),
|
||||
self.rx_ready.eq(comma_aligner.ready_sys),
|
||||
comma_checker.data.eq(rxdata),
|
||||
comma_checker.comma_aligned.eq(comma_aligned),
|
||||
comma_checker.comma_realigned.eq(comma_realigned),
|
||||
comma_checker.comma_det.eq(comma_det),
|
||||
comma_aligner_en.eq(comma_checker.aligner_en),
|
||||
self.rx_ready.eq(comma_checker.ready_sys),
|
||||
|
||||
rx_init.restart.eq(self.rx_restart | comma_checker.restart_sys),
|
||||
tx_init.restart.eq(self.tx_restart),
|
||||
]
|
||||
|
|
|
|||
|
|
@ -2,6 +2,7 @@ from migen import *
|
|||
from migen.genlib.cdc import MultiReg
|
||||
from misoc.interconnect.csr import *
|
||||
from misoc.interconnect import stream
|
||||
from misoc.cores.liteeth_mini.mac.crc import LiteEthMACCRCEngine, LiteEthMACCRCChecker
|
||||
|
||||
from functools import reduce
|
||||
from itertools import combinations
|
||||
|
|
@ -290,6 +291,7 @@ class RX_Debug_Buffer(Module,AutoCSR):
|
|||
class Duplicated_Char_Decoder(Module):
|
||||
def __init__(self):
|
||||
self.sink = stream.Endpoint(word_layout)
|
||||
self.buffer = stream.Endpoint(word_layout)
|
||||
self.source = stream.Endpoint(word_layout_dchar)
|
||||
|
||||
# # #
|
||||
|
|
@ -312,23 +314,22 @@ class Duplicated_Char_Decoder(Module):
|
|||
# Hence, a pipeline approach is needed to avoid any s/h violation, where the majority voting result are pre-calculate and injected into the bus immediate after the PHY.
|
||||
# And any downstream modules can access the voting result without implementing the voting logic inside the decoder
|
||||
|
||||
# cycle 1 - buffer data & calculate intermediate result
|
||||
buffer = stream.Endpoint(word_layout)
|
||||
self.sync += [
|
||||
If((~buffer.stb | buffer.ack),
|
||||
buffer.stb.eq(self.sink.stb),
|
||||
buffer.payload.eq(self.sink.payload),
|
||||
)
|
||||
self.sink.ack.eq(self.buffer.ack),
|
||||
self.buffer.stb.eq(self.sink.stb),
|
||||
If(self.sink.stb,
|
||||
self.buffer.data.eq(self.sink.data),
|
||||
self.buffer.k.eq(self.sink.k),
|
||||
),
|
||||
]
|
||||
self.comb += self.sink.ack.eq(~buffer.stb | buffer.ack)
|
||||
|
||||
# calculate ABC, ABD, ACD, BCD
|
||||
|
||||
# cycle 1 - calculate ABC, ABD, ACD & BCD
|
||||
char = [[self.sink.data[i*8:(i+1)*8], self.sink.k[i]] for i in range(4)]
|
||||
voters = [Record([("data", 8), ("k", 1)]) for _ in range(4)]
|
||||
|
||||
for i, comb in enumerate(combinations(char, 3)):
|
||||
self.sync += [
|
||||
If((~buffer.stb | buffer.ack),
|
||||
If(self.sink.stb,
|
||||
voters[i].data.eq(reduce(and_, [code[0] for code in comb])),
|
||||
voters[i].k.eq(reduce(and_, [code[1] for code in comb])),
|
||||
)
|
||||
|
|
@ -337,16 +338,15 @@ class Duplicated_Char_Decoder(Module):
|
|||
|
||||
# cycle 2 - inject the voting result
|
||||
self.sync += [
|
||||
If((~self.source.stb | self.source.ack),
|
||||
self.source.stb.eq(buffer.stb),
|
||||
self.source.data.eq(buffer.data),
|
||||
self.source.k.eq(buffer.k),
|
||||
self.buffer.ack.eq(self.source.ack),
|
||||
self.source.stb.eq(self.buffer.stb),
|
||||
If(self.buffer.stb,
|
||||
self.source.data.eq(self.buffer.data),
|
||||
self.source.k.eq(self.buffer.k),
|
||||
self.source.dchar.eq(Replicate(reduce(or_, [v.data for v in voters]), 4)),
|
||||
self.source.dchar_k.eq(Replicate(reduce(or_, [v.k for v in voters]), 4)),
|
||||
)
|
||||
),
|
||||
]
|
||||
self.comb += buffer.ack.eq(~self.source.stb | self.source.ack)
|
||||
|
||||
|
||||
@FullMemoryWE()
|
||||
class RX_Bootstrap(Module):
|
||||
|
|
@ -523,3 +523,34 @@ class Trigger_Ack_Checker(Module, AutoCSR):
|
|||
)
|
||||
)
|
||||
)
|
||||
|
||||
@ResetInserter()
|
||||
@CEInserter()
|
||||
class CXPCRC32(Module):
|
||||
# Section 9.2.2.2 (CXP-001-2021)
|
||||
width = 32
|
||||
polynom = 0x04C11DB7
|
||||
seed = 2**width-1
|
||||
check = 0x00000000
|
||||
def __init__(self, data_width):
|
||||
self.data = Signal(data_width)
|
||||
self.value = Signal(self.width)
|
||||
self.error = Signal()
|
||||
|
||||
# # #
|
||||
|
||||
self.submodules.engine = LiteEthMACCRCEngine(data_width, self.width, self.polynom)
|
||||
reg = Signal(self.width, reset=self.seed)
|
||||
self.sync += reg.eq(self.engine.next)
|
||||
self.comb += [
|
||||
self.engine.data.eq(self.data),
|
||||
self.engine.last.eq(reg),
|
||||
|
||||
self.value.eq(reg[::-1]),
|
||||
self.error.eq(self.engine.next != self.check)
|
||||
]
|
||||
|
||||
# For verifying crc in stream data packet
|
||||
class CXPCRC32Checker(LiteEthMACCRCChecker):
|
||||
def __init__(self, layout):
|
||||
LiteEthMACCRCChecker.__init__(self, CXPCRC32, layout)
|
||||
|
|
|
|||
Loading…
Reference in New Issue