forked from M-Labs/artiq-zynq
160 lines
5.6 KiB
Python
160 lines
5.6 KiB
Python
from migen import *
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from misoc.interconnect import stream
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from sim_pipeline import *
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from src.gateware.cxp_pipeline import *
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class CXP_Links(Module):
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def __init__(self):
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# TODO: select the correct buffer to read from
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# NOTE: although there are double buffer in each connect, the reading must be faster than writing to avoid data loss
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self.downconns = []
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for i in range(2):
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downconn = Pipeline()
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setattr(self.submodules, "cxp_conn"+str(i), downconn)
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self.downconns.append(downconn)
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self.submodules.dispatcher = dispatcher = Streams_Dispatcher(self.downconns)
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# TODO: add extractor
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# self.submodules.double_buffer = double_buffer = Double_Stream_Buffer()
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pipeline = [dispatcher]
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for s, d in zip(pipeline, pipeline[1:]):
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self.comb += s.source.connect(d.sink)
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self.source = pipeline[-1].source
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# no backpressure
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self.sync += self.source.ack.eq(1)
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class Pipeline(Module):
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def __init__(self):
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self.submodules.generator = generator = StreamData_Generator()
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self.submodules.dchar_decoder = dchar_decoder = Duplicated_Char_Decoder()
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self.submodules.data_decoder = data_decoder = RX_Bootstrap()
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self.submodules.eop_marker = eop_marker = EOP_Marker()
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# # #
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pipeline = [generator, dchar_decoder, data_decoder, eop_marker]
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for s, d in zip(pipeline, pipeline[1:]):
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self.comb += s.source.connect(d.sink)
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self.sink = pipeline[0].sink
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self.source = pipeline[-1].source
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# self.comb += self.source.ack.eq(1)
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dut = CXP_Links()
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def check_case(packet=[]):
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print("=================TEST========================")
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downconns = dut.downconns
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ch = 0
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for i, p in enumerate(packet):
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for x in range(len(downconns)):
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if x == ch:
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yield downconns[x].sink.data.eq(p["data"])
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yield downconns[x].sink.k.eq(p["k"])
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yield downconns[x].sink.stb.eq(1)
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else:
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yield downconns[x].sink.data.eq(0)
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yield downconns[x].sink.k.eq(0)
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yield downconns[x].sink.stb.eq(0)
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yield downconns[x].sink.eop.eq(0)
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if "eop" in p:
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yield downconns[ch].sink.eop.eq(1)
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# compensate for delay
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# yield
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# yield downconns[ch].sink.data.eq(0)
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# yield downconns[ch].sink.k.eq(0)
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# yield downconns[ch].sink.stb.eq(0)
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# yield downconns[ch].sink.eop.eq(0)
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# yield
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# yield
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# yield
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ch = (ch + 1) % len(downconns)
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else:
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yield downconns[ch].sink.eop.eq(0)
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# check cycle result
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yield
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source = dut.dispatcher.mux.source
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print(
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f"\nCYCLE#{i} : source char = {yield source.data:#X} k = {yield source.k:#X} stb = {yield source.stb} ack = {yield source.ack} eop = {yield source.eop}"
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# f" source dchar = {yield source.dchar:#X} dchar_k = {yield source.dchar_k:#X}"
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f"\nCYCLE#{i} : read mask = {yield dut.dispatcher.mux.sel}"
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# f"\nCYCLE#{i} : stream id = {yield decoder.stream_id:#X} pak_tag = {yield decoder.pak_tag:#X}"
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# f" stream_pak_size = {yield decoder.stream_pak_size:#X}"
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)
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# crc = downconns[1].generator.crc_inserter.crc
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# crc = dut.double_buffer.crc
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# print(
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# f"CYCLE#{i} : crc error = {yield crc.error:#X} crc value = {yield crc.value:#X}"
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# f" crc data = {yield crc.data:#X} engine next = {yield crc.engine.next:#X} ce = {yield crc.ce}"
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# )
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# extra clk cycles
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cyc = i + 1
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for i in range(cyc, cyc + 30):
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for x in range(len(downconns)):
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# yield won't reset every cycle
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yield downconns[x].sink.data.eq(0)
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yield downconns[x].sink.k.eq(0)
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yield downconns[x].sink.stb.eq(0)
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yield downconns[x].sink.eop.eq(0)
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yield
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print(
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f"\nCYCLE#{i} : source char = {yield source.data:#X} k = {yield source.k:#X} stb = {yield source.stb} ack = {yield source.ack} eop = {yield source.eop}"
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# f" source dchar = {yield source.dchar:#X} dchar_k = {yield source.dchar_k:#X}"
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f"\nCYCLE#{i} : read mask = {yield dut.dispatcher.mux.sel}"
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# f"\nCYCLE#{i} : stream id = {yield decoder.stream_id:#X} pak_tag = {yield decoder.pak_tag:#X}"
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# f" stream_pak_size = {yield decoder.stream_pak_size:#X}"
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)
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assert True
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def testbench():
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stream_id = 0x69
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streams = [
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[
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{"data": 0x11111111, "k": Replicate(0, 4)},
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{"data": 0xB105F00D, "k": Replicate(0, 4)},
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],
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[
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{"data": 0x22222222, "k": Replicate(0, 4)},
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{"data": 0xC00010FF, "k": Replicate(0, 4)},
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],
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[
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{"data": 0x33333333, "k": Replicate(0, 4)},
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{"data": 0xC0A79AE5, "k": Replicate(0, 4)},
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],
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]
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packet = []
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for i, s in enumerate(streams):
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s[-1]["eop"] = 0
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packet += [
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{"data": Replicate(C(stream_id, char_width), 4), "k": Replicate(0, 4)},
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{"data": Replicate(C(i, char_width), 4), "k": Replicate(0, 4)},
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{
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"data": Replicate(C(len(s) >> 8 & 0xFF, char_width), 4),
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"k": Replicate(0, 4),
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},
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{"data": Replicate(C(len(s) & 0xFF, char_width), 4), "k": Replicate(0, 4)},
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*s,
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]
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yield from check_case(packet)
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run_simulation(dut, testbench(), vcd_name="sim-cxp.vcd")
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