proto FW: add memory write test

proto FW: fix compilation error

src/gateware/cxp.py

@@ -6,6 +6,9 @@ from cxp_downconn import CXP_DownConn_PHY
 from cxp_upconn import CXP_UpConn_PHY
 from cxp_pipeline import *
 
+buffer_depth = 128
+
+@FullMemoryWE()
 class CXP(Module, AutoCSR):
     def __init__(self, refclk, downconn_pads, upconn_pads, sys_clk_freq, debug_sma, pmod_pads):
         self.submodules.upconn = UpConn_Interface(upconn_pads, sys_clk_freq, debug_sma, pmod_pads)
@@ -13,11 +16,76 @@ class CXP(Module, AutoCSR):
         self.submodules.downconn = DownConn_Interface(refclk, downconn_pads, sys_clk_freq, debug_sma, pmod_pads)
         # TODO: support the option high speed upconn
 
+        self.submodules.transmitter = Transmitter()
+
         # TODO: add link layer
 
+    def get_tx_port(self):
+        return self.transmitter.mem.get_port(write_capable=True)
+    
+    def get_mem_size(self):
+        return buffer_depth*downconn_dw
+
+@FullMemoryWE()
+class Transmitter(Module, AutoCSR):
+    def __init__(self):
+        self.cxp_tx_word_len = CSRStorage(bits_for(buffer_depth))
+        self.cxp_tx = CSR()
+
+        # # #
+        
+        self.specials.mem = mem = Memory(downconn_dw, buffer_depth)
+        self.specials.mem_port = mem_port = mem.get_port()
+        self.source = stream.Endpoint(downconn_layout)
+
+
+        tx_done = Signal()
+        addr_next = Signal(bits_for(buffer_depth))
+        addr = Signal.like(addr_next)
+        addr_rst = Signal()
+        addr_inc = Signal()
+
+        # increment addr in the same cycle the moment addr_inc is rise
+        # since memory takes one cycle to shift to the correct addr
+        self.sync += [
+            addr.eq(addr_next),
+            If(self.cxp_tx.re, self.cxp_tx.w.eq(1)),
+            If(tx_done, self.cxp_tx.w.eq(0)),
+        ]
+
+        self.comb += [
+            addr_next.eq(addr),
+            If(addr_rst,
+                addr_next.eq(addr_next.reset),
+            ).Elif(addr_inc,
+                addr_next.eq(addr + 1),
+            ),
+            mem_port.adr.eq(addr_next),
+            self.source.data.eq(mem_port.dat_r)
+        ]
+
+        self.submodules.fsm = fsm = FSM(reset_state="IDLE")
+
+        fsm.act("IDLE",
+            addr_rst.eq(1),
+            If(self.cxp_tx.re, NextState("TRANSMIT"))
+        )
+        fsm.act("TRANSMIT",
+            self.source.stb.eq(1),
+            If(self.source.ack,
+                addr_inc.eq(1),
+            ),
+            If(addr_next == self.cxp_tx_word_len.storage,
+                tx_done.eq(1),
+                NextState("IDLE")
+            )
+        )
+
+        self.submodules.debug_out = debug_out = RX_Debug_Buffer()
+        self.comb += self.source.connect(debug_out.sink)
+
 class DownConn_Interface(Module, AutoCSR):
     def __init__(self, refclk, downconn_pads, sys_clk_freq, debug_sma, pmod_pads):
-
         # # #
 
         self.submodules.phy = phy = CXP_DownConn_PHY(refclk, downconn_pads, sys_clk_freq, debug_sma, pmod_pads)
@@ -26,16 +94,18 @@ class DownConn_Interface(Module, AutoCSR):
         # DEBUG: TX pipeline
         self.submodules.debug_src = debug_src = TX_Command_Packet()
         self.submodules.trig_ack = trig_ack = Trigger_ACK()
-        self.submodules.mux = mux = stream.Multiplexer(upconn_layout, 2)
-        self.submodules.conv = conv = stream.StrideConverter(upconn_layout, downconn_layout, reverse=True)
+        self.submodules.testseq = testseq = TX_Test_Packet()
+        self.submodules.mux = mux = stream.Multiplexer(upconn_layout, 3)
+        self.submodules.conv = conv = stream.StrideConverter(upconn_layout, downconn_layout)
 
         self.ack = CSR()
-        self.mux_sel = CSRStorage()
+        self.mux_sel = CSRStorage(4)
         self.sync += trig_ack.ack.eq(self.ack.re),
 
         self.comb += [
             debug_src.source.connect(mux.sink0),
             trig_ack.source.connect(mux.sink1),
+            testseq.source.connect(mux.sink2),
             mux.sel.eq(self.mux_sel.storage)
         ]
 
@@ -51,6 +121,16 @@ class DownConn_Interface(Module, AutoCSR):
         for s, d in zip(rx_pipeline, rx_pipeline[1:]):
             self.comb += s.source.connect(d.sink)
 
+
+        self.packet_type = CSRStatus(8)
+        self.decoder_error = CSRStatus()
+        self.test_error = CSRStatus()
+        self.comb += [
+            self.packet_type.status.eq(recv_path.packet_type),
+            self.decoder_error.status.eq(recv_path.decoder_err),
+            self.test_error.status.eq(recv_path.test_err),
+        ]
+        
         # DEBUG: CSR
         self.trig_ack = CSRStatus()
         self.trig_clr = CSR()
@@ -59,6 +139,24 @@ class DownConn_Interface(Module, AutoCSR):
             recv_path.trig_clr.eq(self.trig_clr.re),
         ]
 
+        pak_start = Signal()
+        self.sync += [
+            pak_start.eq(recv_path.packet_decoder.sink.data == 0xFBFBFBFB),
+            
+        ]
+
+        self.specials += [
+            # # pmod 0-7 pin
+            Instance("OBUF", i_I=recv_path.packet_decoder.test_err, o_O=pmod_pads[0]),
+            Instance("OBUF", i_I=pak_start, o_O=pmod_pads[1]),
+            # Instance("OBUF", i_I=fifo_in.source.ack, o_O=pmod_pads[2]),
+            # Instance("OBUF", i_I=gtx.comma_checker.aligner_en, o_O=pmod_pads[3]),
+            # Instance("OBUF", i_I=gtx.comma_checker.check_reset, o_O=pmod_pads[4]),
+            # Instance("OBUF", i_I=gtx.comma_checker.has_comma, o_O=pmod_pads[5]),
+            # Instance("OBUF", i_I=gtx.comma_checker.has_error, o_O=pmod_pads[6]),
+            # Instance("OBUF", i_I=gtx.comma_checker.ready_sys, o_O=pmod_pads[7]),
+        ]
+
         
 class UpConn_Interface(Module, AutoCSR):
     def __init__(self, upconn_pads, sys_clk_freq, debug_sma, pmod_pads):
@@ -81,6 +179,15 @@ class UpConn_Interface(Module, AutoCSR):
         ]
 
 
+        # TODO: rewrite the transmite path into pipeline
+        #
+        # test pak ----+
+        # from gw      |   32                                            32           8
+        #              |---/---> mux -----> trig ack -----> idle word ---/--> conv ---/---> trig -----> PHY
+        #              |                    inserter        inserter                       inserter
+        # data pak ----+
+        # from fw
+
         # Packet FIFOs with transmission priority
         # 0: Trigger packet
         self.submodules.trig = trig = TX_Trigger()

src/gateware/cxp_downconn.py

@@ -106,7 +106,7 @@ class CXP_DownConn_PHY(Module, AutoCSR):
             # DEBUG: remove cdc fifo
             # gtx rx -> fifo out -> cdc out
             
-            fifo_out = stream.AsyncFIFO(downconn_layout, 128)
+            fifo_out = stream.AsyncFIFO(downconn_layout, 512)
             self.submodules += ClockDomainsRenamer({"write": "cxp_gtx_rx", "read": "sys"})(fifo_out)
             self.sources.append(fifo_out)
 
@@ -114,7 +114,7 @@ class CXP_DownConn_PHY(Module, AutoCSR):
                 self.sync.cxp_gtx_rx += [
                     fifo_out.sink.stb.eq(0),
                     # don't store idle word in fifo
-                    If(gtx.rx_ready & fifo_out.sink.ack & (gtx.decoders[0].d != 0xBC),
+                    If((gtx.rx_ready & fifo_out.sink.ack &  ~((gtx.decoders[0].d == 0xBC) & (gtx.decoders[0].k == 1))),
                         fifo_out.sink.stb.eq(1),
                         fifo_out.sink.data[i*8:(i*8)+8].eq(gtx.decoders[i].d),
                         fifo_out.sink.k[i].eq(gtx.decoders[i].k),
@@ -165,7 +165,7 @@ class CXP_DownConn_PHY(Module, AutoCSR):
             # DEBUG: datain
             # fw -> fifo (sys) -> cdc fifo -> gtx tx
             
-            fifo_in = stream.AsyncFIFO(downconn_layout, 128)
+            fifo_in = stream.AsyncFIFO(downconn_layout, 512)
             self.submodules += ClockDomainsRenamer({"write": "sys", "read": "cxp_gtx_tx"})(fifo_in)
             self.sinks.append(fifo_in)
         
@@ -173,16 +173,28 @@ class CXP_DownConn_PHY(Module, AutoCSR):
             txstb = Signal()
             self.specials += MultiReg(self.tx_stb.storage, txstb, odomain="cxp_gtx_tx")
 
+            word_count = Signal(max=100)
+
+            # JANK: fix the every 98th word got eaten
+            # cnt      97    98   99       0
+            # out fifo[97] IDLE IDLE fifo[99]
+            # ack       1     0    0       1
             self.sync.cxp_gtx_tx += [
                 fifo_in.source.ack.eq(0),
-                If(fifo_in.source.stb & txstb,
-                    fifo_in.source.ack.eq(1),
+
+                If(word_count == 99,
+                    word_count.eq(word_count.reset),
+                ).Else(
+                    If(fifo_in.source.stb & txstb,
+                        If(word_count != 98, fifo_in.source.ack.eq(1)),
+                        word_count.eq(word_count + 1),
+                    )
                 )
             ]
 
             # NOTE: prevent the first word send twice due to stream stb delay 
             self.comb += [
-                If(fifo_in.source.stb & fifo_in.source.ack,
+                If((fifo_in.source.stb & fifo_in.source.ack & (word_count != 99)),
                     gtx.encoder.d[0].eq(fifo_in.source.data[:8]),
                     gtx.encoder.d[1].eq(fifo_in.source.data[8:16]),
                     gtx.encoder.d[2].eq(fifo_in.source.data[16:24]),
@@ -211,9 +223,9 @@ class CXP_DownConn_PHY(Module, AutoCSR):
                     # Instance("OBUF", i_I=gtx.cd_cxp_gtx_tx.clk, o_O=debug_sma.n_rx),
 
                     # # pmod 0-7 pin
-                    Instance("OBUF", i_I=txstb, o_O=pmod_pads[0]),
-                    Instance("OBUF", i_I=fifo_in.source.stb, o_O=pmod_pads[1]),
-                    Instance("OBUF", i_I=fifo_in.source.ack, o_O=pmod_pads[2]),
+                    # Instance("OBUF", i_I=txstb, o_O=pmod_pads[0]),
+                    # Instance("OBUF", i_I=fifo_in.source.stb, o_O=pmod_pads[1]),
+                    # Instance("OBUF", i_I=fifo_in.source.ack, o_O=pmod_pads[2]),
                     # Instance("OBUF", i_I=gtx.comma_checker.aligner_en, o_O=pmod_pads[3]),
                     # Instance("OBUF", i_I=gtx.comma_checker.check_reset, o_O=pmod_pads[4]),
                     # Instance("OBUF", i_I=gtx.comma_checker.has_comma, o_O=pmod_pads[5]),

src/gateware/cxp_pipeline.py

@@ -3,6 +3,9 @@ from misoc.interconnect.csr import *
 from misoc.interconnect import stream
 from misoc.cores.liteeth_mini.mac.crc import LiteEthMACCRCEngine, LiteEthMACCRCChecker
 
+
+import struct
+
 upconn_dw = 8
 upconn_layout = [("data", upconn_dw), ("k", upconn_dw//8)]
 
@@ -13,24 +16,32 @@ downconn_layout = [("data", downconn_dw), ("k", downconn_dw//8)]
 def K(x, y):
     return ((y << 5) | x)
 
-def bytes2word(arr):
-    assert len(arr) == 4
-    sum = 0
-    for i, val in enumerate(arr):
-        sum += (val & 0xFF) << i*8
-    return sum 
+KCode = {
+    "pak_start" : K(27, 7),
+    "io_ack" : K(28, 6), 
+    "trig_indic_28_2" : K(28, 2), 
+    "trig_indic_28_4" : K(28, 4), 
+    "pak_end" : K(29, 7),
+}
+
+
+def _bytes2word(bytes, big_endian=True):
+    if big_endian:
+        return struct.unpack(">I", struct.pack(">4B", *bytes))[0]
+    else:
+        return struct.unpack("<I", struct.pack(">4B", *bytes))[0]
 
 class Code_Source(Module):
-    def __init__(self, layout, counts=4):
+    def __init__(self, layout, data, k):
 
         self.source = stream.Endpoint(layout)
         self.stb = Signal()
-        self.data = Signal.like(self.source.data)
-        self.k = Signal.like(self.source.k)
 
         # # #
+        assert len(data) == len(k) > 0
+        counts = len(data)
 
-        cnt = Signal(max=counts)
+        cnt = Signal() if counts == 1 else Signal(max=counts)
         clr_cnt = Signal()
         inc_cnt = Signal()
 
@@ -53,8 +64,8 @@ class Code_Source(Module):
 
         fsm.act("WRITE",
             self.source.stb.eq(1),
-            self.source.data.eq(self.data),
-            self.source.k.eq(self.k),
+            self.source.data.eq(Array(data)[cnt]),
+            self.source.k.eq(Array(k)[cnt]),
             If(cnt == counts - 1,
                 self.source.eop.eq(1),
                 If(self.source.ack, NextState("IDLE"))
@@ -65,7 +76,7 @@ class Code_Source(Module):
 
 
 class Code_Inserter(Module):
-    def __init__(self, layout, insert_infront=True, counts=4):
+    def __init__(self, layout, data, k, insert_infront=True):
         self.sink = stream.Endpoint(layout)
         self.source = stream.Endpoint(layout)
 
@@ -73,7 +84,8 @@ class Code_Inserter(Module):
         self.k = Signal.like(self.sink.k)
 
         # # #
-        assert counts > 0
+        assert len(data) == len(k) > 0
+        counts = len(data)
 
         cnt = Signal() if counts == 1 else Signal(max=counts)
         clr_cnt = Signal()
@@ -88,85 +100,50 @@ class Code_Inserter(Module):
         ]
 
         self.submodules.fsm = fsm = FSM(reset_state="IDLE")
+        remove_sink_oep = 0 if insert_infront else 1
         
-        if insert_infront:
-            fsm.act("IDLE",
-                self.sink.ack.eq(1),
-                clr_cnt.eq(1),
-                If(self.sink.stb,
-                    self.sink.ack.eq(0),
-                    NextState("INSERT"),
-                )
-            )
-
-            fsm.act("INSERT",
+        # add code in front: IDLE -> INSERT -> COPY
+        # add code at end: IDLE -> COPY -> INSERT
+        fsm.act("IDLE",
+            self.sink.ack.eq(1),
+            clr_cnt.eq(1),
+            If(self.sink.stb,
                 self.sink.ack.eq(0),
-                self.source.stb.eq(1),
-                self.source.data.eq(self.data),
-                self.source.k.eq(self.k),
-                If(cnt == counts - 1,
-                    If(self.source.ack, NextState("COPY"))
-                ).Else(
-                    inc_cnt.eq(self.source.ack)
-                )
+                NextState("INSERT" if insert_infront else "COPY"),
             )
+        )
 
-            fsm.act("COPY",
-                self.sink.connect(self.source),
-                If(self.sink.stb & self.sink.eop & self.source.ack,
-                    NextState("IDLE"),
-                )
+        fsm.act("INSERT",
+            self.sink.ack.eq(0),
+            self.source.stb.eq(1),
+            self.source.data.eq(Array(data)[cnt]),
+            self.source.k.eq(Array(k)[cnt]),
+            If(cnt == counts - 1,
+                If(remove_sink_oep, self.source.eop.eq(1)),
+                If(self.source.ack, NextState("COPY" if insert_infront else "IDLE"))
+            ).Else(
+                inc_cnt.eq(self.source.ack)
             )
+        )
 
-        else:
-            fsm.act("IDLE",
-                self.sink.ack.eq(1),
-                clr_cnt.eq(1),
-                If(self.sink.stb,
-                    self.sink.ack.eq(0),
-                    NextState("COPY"),
-                )
-            )
-
-            fsm.act("COPY",
-                self.sink.connect(self.source),
-                self.source.eop.eq(0),
-                If(self.sink.stb & self.sink.eop & self.source.ack,
-                    NextState("INSERT"),
-                )
-            )
-
-            fsm.act("INSERT",
-                self.sink.ack.eq(0),
-                self.source.stb.eq(1),
-                self.source.data.eq(self.data),
-                self.source.k.eq(self.k),
-                If(cnt == counts - 1,
-                    self.source.eop.eq(1),
-                    If(self.source.ack, NextState("IDLE"))
-                ).Else(
-                    inc_cnt.eq(self.source.ack)
-                ),
+        fsm.act("COPY",
+            self.sink.connect(self.source),
+            If(remove_sink_oep, self.source.eop.eq(0)),
+            If(self.sink.stb & self.sink.eop & self.source.ack,
+                NextState("IDLE" if insert_infront else "INSERT"),
             )
+        )
 
 
 class Packet_Wrapper(Module):
     def __init__(self, layout):
-        self.submodules.pak_start = pak_start = Code_Inserter(layout) 
-        self.submodules.pak_end = pak_end = Code_Inserter(layout, insert_infront=False) 
+        self.submodules.pak_start = pak_start = Code_Inserter(layout, [KCode["pak_start"]]*4, [1]*4) 
+        self.submodules.pak_end = pak_end = Code_Inserter(layout, [KCode["pak_end"]]*4, [1]*4, insert_infront=False) 
 
+        self.comb += pak_start.source.connect(pak_end.sink),
         self.sink = pak_start.sink
         self.source = pak_end.source
         
-        self.comb += [
-            pak_start.data.eq(K(27, 7)),
-            pak_start.k.eq(1),
-            pak_end.data.eq(K(29, 7)),
-            pak_end.k.eq(1),
-
-            pak_start.source.connect(pak_end.sink),
-        ]
-        
 @ResetInserter()
 @CEInserter()
 class CXPCRC32(Module):
@@ -205,33 +182,28 @@ class TX_Trigger(Module, AutoCSR):
 
         # # #
 
-        self.submodules.code_src = code_src = Code_Source(upconn_layout, counts=3)
-        self.comb += [
-            code_src.stb.eq(self.trig_stb),
-            code_src.data.eq(self.delay),
-            code_src.k.eq(0)
-        ]
+        # Table 15 & 16 (CXP-001-2021)
+        # Send [K28.2, K28.4, K28.4] or [K28.4, K28.2, K28.2] and 3x delay as trigger packet 
 
-        self.submodules.inserter_once = inserter_once = Code_Inserter(upconn_layout, counts=1)
-        self.submodules.inserter_twice = inserter_twice = Code_Inserter(upconn_layout, counts=2)
-        self.comb += [
-            inserter_once.k.eq(1),
-            inserter_twice.k.eq(1),
+        self.submodules.code_src = code_src = Code_Source(upconn_layout, [self.delay]*3, [0]*3)
+        self.comb += code_src.stb.eq(self.trig_stb),
+
+        header = [Signal(8) for _ in range(3)]
+        self.comb += \
             If((self.linktrig_mode == 0) | (self.linktrig_mode == 2),
-                inserter_once.data.eq(K(28, 2)),
-                inserter_twice.data.eq(K(28, 4)),
+                header[0].eq(KCode["trig_indic_28_2"]),
+                header[1].eq(KCode["trig_indic_28_4"]),
+                header[2].eq(KCode["trig_indic_28_4"]),
             ).Else(
-                inserter_once.data.eq(K(28, 4)),
-                inserter_twice.data.eq(K(28, 2)),
+                header[0].eq(KCode["trig_indic_28_4"]),
+                header[1].eq(KCode["trig_indic_28_2"]),
+                header[2].eq(KCode["trig_indic_28_2"]),
             )
-        ]
         
-        tx_pipeline = [ code_src, inserter_twice, inserter_once]
+        self.submodules.inserter = inserter = Code_Inserter(upconn_layout, header, [1]*3)
 
-        for s, d in zip(tx_pipeline, tx_pipeline[1:]):
-            self.comb += s.source.connect(d.sink)
-
-        self.source = tx_pipeline[-1].source
+        self.comb += code_src.source.connect(inserter.sink)
+        self.source = inserter.source
 
 class Trigger_ACK(Module):
     def __init__(self):
@@ -241,19 +213,14 @@ class Trigger_ACK(Module):
 
         # Section 9.3.2 (CXP-001-2021)
         # Send 4x K28.6 and 4x 0x01 as trigger packet ack
-        self.submodules.code_src = code_src = Code_Source(upconn_layout)
-        self.submodules.k_code_inserter = k_code_inserter = Code_Inserter(upconn_layout)
+        self.submodules.code_src = code_src = Code_Source(upconn_layout, [0x01]*4, [0]*4)
+        self.submodules.inserter = inserter = Code_Inserter(upconn_layout, [KCode["io_ack"]]*4, [1]*4)
         self.comb += [
             code_src.stb.eq(self.ack),
-            code_src.data.eq(0x01),
-            code_src.k.eq(0),
-            k_code_inserter.data.eq(K(28, 6)),
-            k_code_inserter.k.eq(1),
-
-            code_src.source.connect(k_code_inserter.sink)
+            code_src.source.connect(inserter.sink)
         ]
 
-        self.source = k_code_inserter.source
+        self.source = inserter.source
 
 class TX_Command_Packet(Module, AutoCSR):
         # Section 12.1.2 (CXP-001-2021)
@@ -298,63 +265,23 @@ class TX_Test_Packet(Module, AutoCSR):
 
         # # #
 
-        testdata_src = stream.Endpoint(upconn_layout)
-
-        
-        # Section 9.9.2 (CXP-001-2021)
-        # 0x00, 0x01 ... 0xFF need to be send 16 times 
-        # cnt[8:12] is used to count up 16 times while cnt[:8] is the data 
-        cnt = Signal(max=0x1000)
-        clr_cnt = Signal()
-        inc_cnt = Signal()
-
-        self.sync += [
-            If(clr_cnt,
-                cnt.eq(cnt.reset),
-            ).Elif(inc_cnt,
-                cnt.eq(cnt + 1),
-            ),
-        ]
-
-        self.submodules.fsm = fsm = FSM(reset_state="IDLE")
-        
-        fsm.act("IDLE",
-            clr_cnt.eq(1),
-            If(self.stb.re,
-               NextState("WRITE")
-            )
-        )
-
-        fsm.act("WRITE",
-            testdata_src.stb.eq(1),
-            testdata_src.data.eq(cnt[:8]),
-            testdata_src.k.eq(0),
-            If(cnt == 0xFFF,
-                testdata_src.eop.eq(1),
-                If(testdata_src.ack, NextState("IDLE"))
-            ).Else(
-                inc_cnt.eq(testdata_src.ack)
-            )
-        )
-
-        self.submodules.pak_type_inserter = pak_type_inserter = Code_Inserter(upconn_layout)
+        self.submodules.test_pattern_src = test_pattern_src = Code_Source(upconn_layout, [*range(0x100)]*16, [0]*0x100*16)
+        self.submodules.pak_type_inserter = pak_type_inserter = Code_Inserter(upconn_layout, [0x04]*4, [0]*4)
         self.submodules.pak_wrp = pak_wrp = Packet_Wrapper(upconn_layout)
         self.comb += [
-            pak_type_inserter.data.eq(0x04),
-            pak_type_inserter.k.eq(0),
-
-            testdata_src.connect(pak_type_inserter.sink),
+            test_pattern_src.source.connect(pak_type_inserter.sink),
             pak_type_inserter.source.connect(pak_wrp.sink),
         ]
 
         self.source = pak_wrp.source
-
-        self.sync += \
+        self.sync += [
+            test_pattern_src.stb.eq(self.stb.re),
             If(self.stb.re,
                 self.busy.status.eq(1),
             ).Elif(self.source.eop & self.source.ack,
                 self.busy.status.eq(0)
             )
+        ]
 
 class RX_Debug_Buffer(Module,AutoCSR):
     def __init__(self):
@@ -379,8 +306,52 @@ class Receiver_Path(Module, AutoCSR):
         self.trig_ack = Signal()
         self.trig_clr = Signal()
 
-        # TODO:
         self.packet_type = Signal(8)
+        self.decoder_err = Signal()
+        self.decoder_err_clr = Signal()
+
+        self.test_err = Signal()
+        self.test_err_clr = Signal()
+
+        # # #
+
+        
+        self.submodules.trig_ack_checker = trig_ack_checker = CXP_Trig_Ack_Checker()
+        self.submodules.packet_decoder = packet_decoder = CXP_Data_Packet_Decode()
+
+        # Error are latched
+        self.sync += [
+            If(trig_ack_checker.ack,
+                self.trig_ack.eq(1),
+            ).Elif(self.trig_clr,
+                self.trig_ack.eq(0),
+            ),
+
+            If(packet_decoder.decode_err,
+                self.decoder_err.eq(1),
+            ).Elif(self.decoder_err_clr,
+                self.decoder_err.eq(0),
+            ),
+
+            If(packet_decoder.test_err,
+                self.test_err.eq(1),
+            ).Elif(self.test_err_clr,
+                self.test_err.eq(0),
+            )
+        ]
+        self.comb += [
+            self.packet_type.eq(packet_decoder.packet_type),
+            
+        ]
+
+        pipeline = [ trig_ack_checker, packet_decoder ]
+
+        for s, d in zip(pipeline, pipeline[1:]):
+            self.comb += s.source.connect(d.sink)
+
+        self.sink = pipeline[0].sink
+        self.source = pipeline[-1].source
+
 
     
 class CXP_Data_Packet_Decode(Module):
@@ -389,9 +360,111 @@ class CXP_Data_Packet_Decode(Module):
         # This is where data stream comes out
         self.source = stream.Endpoint(downconn_layout)
 
+        self.packet_type = Signal(8)
+        self.decode_err = Signal()
+
+        self.buffer = Signal(40*downconn_dw)
+        self.test_err = Signal()
         # # #
 
-        self.comb += self.sink.connect(self.source)
+        # decoder -> priorities mux(normal packet vs trigger ack) -> data packet mux (control ack, data stream, heartbeat, testmode, (optional Genlcam event))
+        type = {
+            "data_stream": 0x01,
+            "control_ack_no_tag": 0x03,
+            "test_packet": 0x04,
+            "control_ack_with_tag": 0x06,
+            "event_ack": 0x08,
+            "heartbeat": 0x09,
+
+            "debug" : 0x02,
+        }
+
+        self.submodules.fsm = fsm = FSM(reset_state="IDLE")
+
+        fsm.act("IDLE",
+            self.sink.ack.eq(1),
+            # TODO: add error correction?
+            If((self.sink.stb & (self.sink.data == _bytes2word([KCode["pak_start"]]*4)) & (self.sink.k == 0b1111)),
+                NextState("DECODE"),
+            )
+        )
+
+        # TODO: decode all packet type here
+
+        cnt = Signal(max=0x100)
+
+        fsm.act("DECODE",
+            self.sink.ack.eq(1),
+            If(self.sink.stb,
+                NextValue(self.packet_type, self.sink.data[:8]),
+
+                Case(self.sink.data[:8],{
+                    type["data_stream"]: NextState("STREAMING"),
+                    type["debug"]: NextState("STREAMING"),
+                    type["test_packet"]: [
+                        NextValue(cnt, 0),
+                        NextState("VERIFY_TEST_PATTERN"),
+                    ],
+                    "default": [
+                         self.decode_err.eq(1),
+                         # wait till next valid packet
+                         NextState("IDLE"),
+                    ],
+                }),
+            )
+        )
+
+        # Section 9.9.1 (CXP-001-2021)
+        # the received test data packet (0x00, 0x01 ... 0xFF) 
+        # need to be compared against the local test sequence generator
+        fsm.act("VERIFY_TEST_PATTERN",
+            self.sink.ack.eq(1),
+            If(self.sink.stb,
+                If(((self.sink.data == _bytes2word([KCode["pak_end"]]*4)) & (self.sink.k == 0b1111)),
+                    NextState("IDLE"),
+                ).Else(
+                    If(((self.sink.data != Cat(cnt, cnt+1, cnt+2, cnt+3))),  
+                       self.test_err.eq(1),
+                    ),
+                    If(cnt == 0xFC,
+                        NextValue(cnt, cnt.reset),
+                    ).Else(
+                        NextValue(cnt, cnt + 4)
+                    )
+                )
+            )
+                
+        )
+
+        fsm.act("STREAMING",
+            If((self.sink.stb & (self.sink.data == _bytes2word([KCode["pak_end"]]*4)) & (self.sink.k == 0b1111)),
+                # discard K29,7
+                self.sink.ack.eq(1),
+                NextState("IDLE")
+            ).Else(
+                self.sink.connect(self.source),
+            )      
+        )
+        # # input pipeline stage - determine packet length based on type
+        # self.sync += [
+        #     packet_start.eq((self.sink.data[0] == K(27, 7)) & (self.sink.k[0] == 1)),
+        #     packet_end.eq((self.sink.data[0] == K(29, 7)) & (self.sink.k[0] == 1)),
+
+        #     If((self.sink.data[0] == K(27, 7)) & (self.sink.k[0] == 1),
+        #        packet_buffer_load.eq(1),
+        #     ),
+
+
+        #     trig_ack.eq((self.sink.data[0] == K(28, 6)) & (self.sink.k[0] == 1)),
+        #     If(trig_ack,
+        #         self.trig_ack.eq(self.sink.data[0]),
+        #         trig_ack.eq(0),
+        #     ).Elif(packet_buffer_load,
+        #         # TODO: add test packet counting
+        #         Case(buffer_count,
+        #              {i: buffer[i*downconn_dw:(i+1)*downconn_dw].eq(self.sink.data)
+        #               for i in range(40)}),
+        #         buffer_count.eq(buffer_count + 1),
 
 
 class CXP_Trig_Ack_Checker(Module, AutoCSR):
@@ -414,7 +487,7 @@ class CXP_Trig_Ack_Checker(Module, AutoCSR):
         )
 
         fsm.act("COPY",
-            If((self.sink.stb & (self.sink.data == bytes2word([K(28, 6)]*4)) & (self.sink.k == 0b1111)),
+            If((self.sink.stb & (self.sink.data == _bytes2word([KCode["io_ack"]]*4)) & (self.sink.k == 0b1111)),
                 # discard K28,6
                 self.sink.ack.eq(1),
                 NextState("CHECK_ACK")
@@ -428,7 +501,7 @@ class CXP_Trig_Ack_Checker(Module, AutoCSR):
                 NextState("IDLE"),
                 # discard the word after K28,6
                 self.sink.ack.eq(1),
-                If(self.sink.data == bytes2word([0x01]*4),
+                If(self.sink.data == _bytes2word([0x01]*4),
                     self.ack.eq(1),
                 )
             )

src/gateware/zc706.py

@@ -698,6 +698,15 @@ class CXP_FMC():
         )
         self.csr_devices.append("cxp")
 
+        # TODO: add memory for tx & rx CXP
+        memory_name = "cxp_tx"
+        mem_size = self.cxp.get_mem_size()
+        memory_address = self.axi2csr.register_port(self.cxp.get_tx_port(), mem_size)
+        self.add_memory_region(memory_name, self.mem_map["csr"] + memory_address, mem_size)
+        cxp_memory_group = [ memory_name ]
+        self.add_memory_group("cxp_mem", cxp_memory_group)
+
+
         # max freq of cxp_gtx_rx = linerate/internal_datawidth = 12.5Gbps/40 = 312.5MHz
         # zc706 use speed grade 2 which only support up to 10.3125Gbps (4ns)
         # pushing to 12.5Gbps (3.2ns) will result in Pulse width violation but setup/hold times are met

src/libboard_artiq/src/cxp_downconn.rs

@@ -37,7 +37,12 @@ pub fn loopback_testing(timer: &mut GlobalTimer, speed: CXP_SPEED) {
         while csr::cxp::downconn_phy_rx_ready_read() != 1 {}
         info!("rx ready!");
 
-        cxp_proto::downconn_debug_send_trig_ack();
+        csr::cxp::downconn_phy_tx_stb_write(1);
+        cxp_proto::downconn_send_test_packet();
+        timer.delay_us(20000); // wait packet has arrive at rx
+        csr::cxp::downconn_phy_tx_stb_write(0);
+
+        // cxp_proto::downconn_debug_send_trig_ack();
 
         cxp_proto::downconn_debug_send(&cxp_proto::Packet::CtrlRead {
             addr: 0x00,
@@ -53,6 +58,10 @@ pub fn loopback_testing(timer: &mut GlobalTimer, speed: CXP_SPEED) {
         csr::cxp::downconn_trig_clr_write(1);
         info!("after clr trig ack = {}", csr::cxp::downconn_trig_ack_read());
 
+        info!("decoder error = {}", csr::cxp::downconn_decoder_error_read());
+        info!("test error = {}", csr::cxp::downconn_test_error_read());
+        info!("packet type = {:#06X}", csr::cxp::downconn_packet_type_read());
+
         // TODO: investigate how to make my packet appear
         // TODO: discard idle word
 

src/libboard_artiq/src/cxp_proto.rs

@@ -1,10 +1,12 @@
+use core::slice;
+
 use core_io::{Error as IoError, Write};
 use crc::crc32;
 use embedded_hal::prelude::_embedded_hal_blocking_delay_DelayUs;
 use io::Cursor;
 use libboard_zynq::{println, timer::GlobalTimer};
 
-use crate::pl::csr;
+use crate::{mem::mem::CXP_MEM, pl::csr};
 
 const MAX_PACKET: usize = 128;
 const DATA_MAXSIZE: usize = /*max size*/MAX_PACKET - /*Tag*/4 - /*Op code & length*/4 - /*addr*/4 - /*CRC*/4 ;
@@ -137,7 +139,6 @@ fn send_test_packet() -> Result<(), Error> {
     unsafe {
         while csr::cxp::upconn_tx_busy_read() == 1 {}
         csr::cxp::upconn_tx_testmode_en_write(1);
-        // timer.delay_us(2);
         csr::cxp::upconn_testseq_stb_write(1);
         while csr::cxp::upconn_testseq_busy_read() == 1 {}
         csr::cxp::upconn_tx_testmode_en_write(0);
@@ -195,7 +196,7 @@ pub fn print_packet(pak: &[u8]) {
 pub fn print_packetu32(pak: &[u32], k: &[u8]) {
     println!("pak = [");
     for i in 0..(pak.len()) {
-        let data: [u8; 4] = pak[i].to_be_bytes();
+        let data: [u8; 4] = pak[i].to_le_bytes();
         println!(
             "{:#03}     {:#04X} {:#04X} {:#04X} {:#04X} | K {:04b},",
             i + 1,
@@ -236,3 +237,45 @@ pub fn downconn_debug_send_trig_ack() {
         csr::cxp::downconn_ack_write(1);
     }
 }
+
+pub fn downconn_send_test_packet() {
+    unsafe {
+        csr::cxp::downconn_mux_sel_write(2);
+        csr::cxp::downconn_testseq_stb_write(1);
+        while csr::cxp::downconn_testseq_busy_read() == 1 {}
+    }
+}
+
+pub fn ram_writer_send(packet: &Packet) -> Result<(), Error> {
+    unsafe {
+        // TODO: put this in mem group
+        while csr::cxp::transmitter_cxp_tx_read() == 1 {}
+        let ptr = CXP_MEM[0].base as *mut u32;
+        let mut writer = Cursor::new(slice::from_raw_parts_mut(ptr as *mut u8, 0x200 as usize));
+
+        packet.write_to(&mut writer)?;
+
+        csr::cxp::transmitter_cxp_tx_word_len_write(writer.position() as u8 / 4);
+        csr::cxp::transmitter_cxp_tx_write(1);
+        while csr::cxp::transmitter_cxp_tx_read() == 1 {}
+
+        // read the fifo
+        const LEN: usize = 10;
+        let mut pak_arr: [u32; LEN] = [0; LEN];
+        let mut k_arr: [u8; LEN] = [0; LEN];
+        let mut i: usize = 0;
+        while csr::cxp::transmitter_debug_out_dout_valid_read() == 1 {
+            pak_arr[i] = csr::cxp::transmitter_debug_out_dout_pak_read();
+            k_arr[i] = csr::cxp::transmitter_debug_out_kout_pak_read();
+            // println!("received {:#04X}", pak_arr[i]);
+            csr::cxp::transmitter_debug_out_inc_write(1);
+            i += 1;
+            if i == LEN {
+                break;
+            }
+        }
+        print_packetu32(&pak_arr, &k_arr);
+    }
+
+    Ok(())
+}

src/runtime/src/main.rs

@@ -17,7 +17,7 @@ use libasync::task;
 use libboard_artiq::drtio_eem;
 #[cfg(feature = "target_kasli_soc")]
 use libboard_artiq::io_expander;
-use libboard_artiq::{identifier_read, logger, pl};
+use libboard_artiq::{cxp_downconn, cxp_proto, cxp_upconn, identifier_read, logger, pl};
 use libboard_zynq::{gic, mpcore, timer::GlobalTimer};
 use libconfig::Config;
 use libcortex_a9::l2c::enable_l2_cache;
@@ -150,16 +150,19 @@ pub fn main_core0() {
 
     task::spawn(ksupport::report_async_rtio_errors());
 
-    use libboard_artiq::{cxp_downconn, cxp_upconn};
     cxp_downconn::setup(&mut timer);
-    // cxp_downconn::loopback_testing(&mut timer, cxp_downconn::CXP_SPEED::CXP_1);
+    cxp_downconn::loopback_testing(&mut timer, cxp_downconn::CXP_SPEED::CXP_1);
     // cxp_downconn::loopback_testing(&mut timer, cxp_downconn::CXP_SPEED::CXP_2);
     // cxp_downconn::loopback_testing(&mut timer, cxp_downconn::CXP_SPEED::CXP_3);
     // cxp_downconn::loopback_testing(&mut timer, cxp_downconn::CXP_SPEED::CXP_5);
     // cxp_downconn::loopback_testing(&mut timer, cxp_downconn::CXP_SPEED::CXP_6);
     // cxp_downconn::loopback_testing(&mut timer, cxp_downconn::CXP_SPEED::CXP_10);
     // cxp_downconn::loopback_testing(&mut timer, cxp_downconn::CXP_SPEED::CXP_12);
-    cxp_upconn::tx_test(&mut timer);
+    // loop {
+    //     use embedded_hal::prelude::_embedded_hal_blocking_delay_DelayUs;
+    //     cxp_upconn::tx_test(&mut timer);
+    //     timer.delay_us(5_000_000);
+    // }
 
     comms::main(timer, cfg);
 }