api: add cxp api support for CTRL packet

proto FW: general cleanup & update csr names

flake.lock

@@ -116,10 +116,27 @@
         "type": "github"
       }
     },
+    "nixpkgs_old": {
+      "locked": {
+        "lastModified": 1720535198,
+        "narHash": "sha256-zwVvxrdIzralnSbcpghA92tWu2DV2lwv89xZc8MTrbg=",
+        "owner": "nixos",
+        "repo": "nixpkgs",
+        "rev": "205fd4226592cc83fd4c0885a3e4c9c400efabb5",
+        "type": "github"
+      },
+      "original": {
+        "owner": "nixos",
+        "ref": "nixos-23.11",
+        "repo": "nixpkgs",
+        "type": "github"
+      }
+    },
     "root": {
       "inputs": {
         "artiq": "artiq",
         "mozilla-overlay": "mozilla-overlay",
+        "nixpkgs_old": "nixpkgs_old",
         "zynq-rs": "zynq-rs"
       }
     },

flake.nix

@@ -6,12 +6,16 @@
   inputs.zynq-rs.url = git+https://git.m-labs.hk/m-labs/zynq-rs;
   inputs.zynq-rs.inputs.nixpkgs.follows = "artiq/nixpkgs";
 
-  outputs = { self, mozilla-overlay, zynq-rs, artiq }:
+  inputs.nixpkgs_old.url = "github:nixos/nixpkgs?ref=nixos-23.11";
+
+  outputs = { self, mozilla-overlay, zynq-rs, artiq, nixpkgs_old }:
   let
+    pkgs_old = import nixpkgs_old { system = "x86_64-linux";};
     pkgs = import artiq.inputs.nixpkgs { system = "x86_64-linux"; overlays = [ (import mozilla-overlay) ]; };
     zynqpkgs = zynq-rs.packages.x86_64-linux;
     artiqpkgs = artiq.packages.x86_64-linux;
-    llvmPackages_11 = zynq-rs.llvmPackages_11;
+    # llvmPackages_11 = zynq-rs.llvmPackages_11;
+    llvmPackages_11 = pkgs_old.llvmPackages_11;
 
     rust = zynq-rs.rust;
     rustPlatform = zynq-rs.rustPlatform;

local_run.sh

@@ -13,7 +13,7 @@ fi
 
 impure=0
 load_bitstream=1
-board_type="kasli_soc"
+board_type="zc706"
 fw_type="runtime"
 
 while getopts "ilb:t:f:" opt; do
@@ -36,7 +36,7 @@ done
 if [ -z "$board_host" ]; then
     case $board_type in
     kasli_soc) board_host="192.168.1.56";;
-    zc706) board_host="192.168.1.52";;
+    zc706) board_host="192.168.1.14";;
     *) echo "Unknown board type"; exit 1;;
     esac
 fi
@@ -58,4 +58,4 @@ else
         load_bitstream_cmd="-g $result_dir/top.bit"
     fi
     artiq_netboot $load_bitstream_cmd -f $result_dir/$fw_type.bin -b $board_host
-fi
+fi

src/gateware/cxp.py

@@ -16,29 +16,32 @@ class CXP_PHYS(Module, AutoCSR):
 @FullMemoryWE()
 class CXP_Interface(Module, AutoCSR):
     def __init__(self, upconn_phy, downconn_phy, debug_sma, pmod_pads):
-        # TODO: move all transceiver csr into a transceiver interface submodule
+        # TODO: add rtio interface io 
         
         self.submodules.upconn = UpConn_Interface(upconn_phy, debug_sma, pmod_pads)
 
         self.submodules.downconn = DownConn_Interface(downconn_phy, debug_sma, pmod_pads)
 
     def get_tx_port(self):
-        return self.upconn.command.mem.get_port(write_capable=True)
+        return self.upconn.bootstrap.mem.get_port(write_capable=True)
 
     def get_tx_mem_size(self):
-        return self.upconn.command.mem.depth*self.upconn.command.mem.width
+        # FIXME: if tx mem size is same as rx, for some reason when rx mem is writen, tx mem cannot be access anymore
+        # and each time tx mem is read, CPU will return rx mem instead
+        return self.upconn.bootstrap.mem.depth*self.upconn.bootstrap.mem.width // 8
+        # return self.downconn.bootstrap.mem.depth*self.downconn.bootstrap.mem.width // 8
 
     def get_rx_port(self):
-        return self.downconn.packet_decoder.mem.get_port(write_capable=False)
+        return self.downconn.bootstrap.mem.get_port(write_capable=False)
 
     def get_rx_mem_size(self):
-        return self.downconn.packet_decoder.mem.depth*self.downconn.packet_decoder.mem.width
+        return self.downconn.bootstrap.mem.depth*self.downconn.bootstrap.mem.width // 8
 
     def get_loopback_tx_port(self):
-        return self.downconn.command.mem.get_port(write_capable=True)
+        return self.downconn.bootstrap_loopback.mem.get_port(write_capable=True)
     
     def get_loopback_tx_mem_size(self):
-        return self.downconn.command.mem.depth*self.downconn.command.mem.width
+        return self.downconn.bootstrap_loopback.mem.depth*self.downconn.bootstrap_loopback.mem.width // 8
 
 class DownConn_Interface(Module, AutoCSR):
     def __init__(self, phy, debug_sma, pmod_pads):
@@ -149,17 +152,17 @@ class DownConn_Interface(Module, AutoCSR):
 
         # DEBUG: Transmission Pipeline
         # 
-        # test pak ----+
-        # from gw      |   32                                            32
-        #              |---/---> mux -----> packet -----> trigger ack ---/---> PHY
-        #              |                    wrapper       inserter
-        # data pak ----+
-        # from fw
+        #  rtio pak  ----+
+        #   from gw      |   32                                  32
+        #               mux---/---> packet -----> trigger ack ---/---> PHY
+        #                |          wrapper       inserter
+        #  data/test ----+
+        #  pak from fw
+        #
         
 
         # DEBUG: TX pipeline
-        self.submodules.command = command = TX_Command_Packet()
-        self.submodules.testseq = testseq = TX_Test_Packet()
+        self.submodules.bootstrap_loopback = bootstrap_loopback = TX_Bootstrap()
         self.submodules.mux = mux = stream.Multiplexer(word_layout, 2)
         self.submodules.pak_wrp = pak_wrp = Packet_Wrapper()
         self.submodules.trig_ack = trig_ack = Trigger_ACK_Inserter()
@@ -169,8 +172,7 @@ class DownConn_Interface(Module, AutoCSR):
 
         self.sync += trig_ack.stb.eq(self.ack.re),
         self.comb += [
-            command.source.connect(mux.sink0),
-            testseq.source.connect(mux.sink1),
+            bootstrap_loopback.source.connect(mux.sink0),
             mux.sel.eq(self.mux_sel.storage),
         ]
 
@@ -207,36 +209,36 @@ class DownConn_Interface(Module, AutoCSR):
         ]
 
         # Priority level 2 packet - data, test packet
-        self.submodules.packet_decoder = packet_decoder = cdr(CXP_Data_Packet_Decode())
+        self.submodules.bootstrap = bootstrap = cdr(RX_Bootstrap())
 
-        self.decoder_error = CSR()
-        self.test_error = CSR()
-        self.buffer_error = CSR()
+        self.bootstrap_decoder_err = CSR()
+        self.bootstrap_test_err = CSR()
+        self.boostrap_buffer_err = CSR()
 
         decode_err_ps = PulseSynchronizer("cxp_gtx_rx", "sys")
         test_err_ps = PulseSynchronizer("cxp_gtx_rx", "sys")
         buffer_err_ps = PulseSynchronizer("cxp_gtx_rx", "sys")
         self.submodules += decode_err_ps, test_err_ps, buffer_err_ps
         self.comb += [
-            decode_err_ps.i.eq(packet_decoder.decode_err),
-            test_err_ps.i.eq(packet_decoder.test_err),
-            buffer_err_ps.i.eq(packet_decoder.buffer_err),
+            decode_err_ps.i.eq(bootstrap.decode_err),
+            test_err_ps.i.eq(bootstrap.test_err),
+            buffer_err_ps.i.eq(bootstrap.buffer_err),
         ]
         self.sync += [
             If(decode_err_ps.o,
-                self.decoder_error.w.eq(1),
-            ).Elif(self.decoder_error.re,
-                self.decoder_error.w.eq(0),
+                self.bootstrap_decoder_err.w.eq(1),
+            ).Elif(self.bootstrap_decoder_err.re,
+                self.bootstrap_decoder_err.w.eq(0),
             ),
             If(test_err_ps.o,
-                self.test_error.w.eq(1),
-            ).Elif(self.test_error.re,
-                self.test_error.w.eq(0),
+                self.bootstrap_test_err.w.eq(1),
+            ).Elif(self.bootstrap_test_err.re,
+                self.bootstrap_test_err.w.eq(0),
             ),
             If(buffer_err_ps.o,
-                self.buffer_error.w.eq(1),
-            ).Elif(self.test_error.re,
-                self.buffer_error.w.eq(0),
+                self.boostrap_buffer_err.w.eq(1),
+            ).Elif(self.bootstrap_test_err.re,
+                self.boostrap_buffer_err.w.eq(0),
             ),
         ]
 
@@ -247,12 +249,14 @@ class DownConn_Interface(Module, AutoCSR):
         self.read_ptr = CSRStatus(log2_int(buffer_count))
 
         self.specials += [
-            MultiReg(packet_decoder.packet_type, self.packet_type.status),
-            MultiReg(self.read_ptr.status, packet_decoder.read_ptr_rx, odomain="cxp_gtx_rx"),
+            MultiReg(bootstrap.packet_type, self.packet_type.status),
+            MultiReg(self.read_ptr.status, bootstrap.read_ptr_rx, odomain="cxp_gtx_rx"),
         ]
         self.sync += [
-            self.pending_packet.w.eq(self.read_ptr.status != packet_decoder.write_ptr_sys),
-            If(self.pending_packet.re & self.pending_packet.w, 
+            self.pending_packet.w.eq(self.read_ptr.status != bootstrap.write_ptr_sys),
+            If(self.rx_restart.re,
+                self.read_ptr.status.eq(0),
+            ).Elif(self.pending_packet.re & self.pending_packet.w, 
                 self.read_ptr.status.eq(self.read_ptr.status + 1),
             )
         ]
@@ -263,8 +267,18 @@ class DownConn_Interface(Module, AutoCSR):
         self.submodules += ClockDomainsRenamer({"write": "cxp_gtx_rx", "read": "sys"})(cdc_fifo)
         self.submodules.debug_out = debug_out = RX_Debug_Buffer()
 
+        self.dmux_sel = CSRStorage()
+        self.submodules.dmux = dmux = stream.Demultiplexer(word_layout, 2)
 
-        rx_pipeline = [phy, trig_ack_checker, packet_decoder, cdc_fifo, debug_out]
+
+        self.comb += [
+            dmux.source0.connect(bootstrap.sink),
+            dmux.source1.connect(cdc_fifo.sink),
+            cdc_fifo.source.connect(debug_out.sink),
+            dmux.sel.eq(self.dmux_sel.storage),
+        ]
+
+        rx_pipeline = [phy, trig_ack_checker, dmux]
         for s, d in zip(rx_pipeline, rx_pipeline[1:]):
             self.comb += s.source.connect(d.sink)
         
@@ -278,14 +292,14 @@ class DownConn_Interface(Module, AutoCSR):
 
         pak_start = Signal()
         self.sync += [
-            pak_start.eq(packet_decoder.sink.data == 0xFBFBFBFB),
+            pak_start.eq(bootstrap.sink.data == 0xFBFBFBFB),
         ]
 
         self.specials += [
             Instance("OBUF", i_I=phy.gtx.cd_cxp_gtx_rx.clk, o_O=debug_sma.p_tx),
             # Instance("OBUF", i_I=, o_O=debug_sma.p_rx),
             # # pmod 0-7 pin
-            Instance("OBUF", i_I=packet_decoder.test_err, o_O=pmod_pads[0]),
+            Instance("OBUF", i_I=bootstrap.test_err, o_O=pmod_pads[0]),
             Instance("OBUF", i_I=pak_start, o_O=pmod_pads[1]),
             # Instance("OBUF", i_I=fifo_in.source.ack, o_O=pmod_pads[2]),
             # Instance("OBUF", i_I=gtx.comma_checker.aligner_en, o_O=pmod_pads[3]),
@@ -301,11 +315,7 @@ class UpConn_Interface(Module, AutoCSR):
         self.clk_reset = CSRStorage(reset=1)
         self.bitrate2x_enable = CSRStorage()
         self.tx_enable = CSRStorage()
-
-        # TODO: add busy condition
-        self.tx_busy = CSRStatus()
-
-        self.tx_testmode_en = CSRStorage()
+        self.tx_mux = CSRStorage()
 
         # # #
 
@@ -317,13 +327,10 @@ class UpConn_Interface(Module, AutoCSR):
 
 
         # Transmission Pipeline
-        # 
-        # test pak ----+
-        # from gw      |   32                                                             32           8
-        #              |---/---> mux -----> packet -----> idle word -----> trigger ack ---/--> conv ---/---> trigger -----> PHY
-        #              |                    wrapper       inserter         inserter                          inserter
-        # data pak ----+
-        # from fw
+        #
+        #              32                                                  32           8
+        # ctrl/test ---/---> packet -----> idle word -----> trigger ack ---/--> conv ---/---> trigger -----> PHY
+        # packet             wrapper       inserter         inserter                          inserter
         #
         # Equivalent transmission priority:
         # trigger > trigger ack > idle > test/data packet
@@ -362,20 +369,9 @@ class UpConn_Interface(Module, AutoCSR):
 
         # 2: All other packets (data & test packet)
         # Control is not timing dependent, all the data packets are handled in firmware
-
-        self.submodules.command = command = TX_Command_Packet()
-        self.submodules.testseq = testseq = TX_Test_Packet()
-        self.submodules.mux = mux = stream.Multiplexer(word_layout, 2)
-
-        self.comb += [
-            command.source.connect(mux.sink0),
-            testseq.source.connect(mux.sink1),
-            mux.sel.eq(self.tx_testmode_en.storage),
-        ]
+        self.submodules.bootstrap = bootstrap = TX_Bootstrap()
 
         self.submodules.pak_wrp = pak_wrp = Packet_Wrapper()
-
-        # IDLE Word
         self.submodules.idle = idle = Idle_Word_Inserter()
 
         # Section 9.2.5.1 (CXP-001-2021)
@@ -394,6 +390,6 @@ class UpConn_Interface(Module, AutoCSR):
         
         self.submodules.converter = converter = stream.StrideConverter(word_layout, char_layout)
 
-        tx_pipeline = [mux, pak_wrp, idle, trig_ack, converter, trig, phy]
+        tx_pipeline = [bootstrap, pak_wrp, idle, trig_ack, converter, trig, phy]
         for s, d in zip(tx_pipeline, tx_pipeline[1:]):
             self.comb += s.source.connect(d.sink)

src/gateware/cxp_pipeline.py

@@ -180,10 +180,13 @@ class Trigger_ACK_Inserter(Module):
 
 
 @FullMemoryWE()
-class TX_Command_Packet(Module, AutoCSR):
+class TX_Bootstrap(Module, AutoCSR):
     def __init__(self):
         self.tx_word_len = CSRStorage(log2_int(buffer_depth))
         self.tx = CSR()
+        self.tx_testseq = CSR()
+
+        self.tx_busy = CSRStatus()
 
         # # #
         
@@ -191,20 +194,13 @@ class TX_Command_Packet(Module, AutoCSR):
         self.specials.mem_port = mem_port = mem.get_port()
         self.source = stream.Endpoint(word_layout)
 
-
-        tx_done = Signal()
+        # increment addr in the same cycle the moment addr_inc is high
+        # as memory takes one cycle to shift to the correct addr
         addr_next = Signal(log2_int(buffer_depth))
         addr = Signal.like(addr_next)
         addr_rst = Signal()
         addr_inc = Signal()
-
-        # increment addr in the same cycle the moment addr_inc is high
-        # as memory takes one cycle to shift to the correct addr
-        self.sync += [
-            addr.eq(addr_next),
-            If(self.tx.re, self.tx.w.eq(1)),
-            If(tx_done, self.tx.w.eq(0)),
-        ]
+        self.sync += addr.eq(addr_next),
 
         self.comb += [
             addr_next.eq(addr),
@@ -218,11 +214,18 @@ class TX_Command_Packet(Module, AutoCSR):
         ]
 
         self.submodules.fsm = fsm = FSM(reset_state="IDLE")
+        self.sync += self.tx_busy.status.eq(~fsm.ongoing("IDLE"))
 
+        cnt = Signal(max=0xFFF)
         fsm.act("IDLE",
             addr_rst.eq(1),
-            If(self.tx.re, NextState("TRANSMIT"))
+            If(self.tx.re, NextState("TRANSMIT")),
+            If(self.tx_testseq.re, 
+                NextValue(cnt, cnt.reset),
+                NextState("WRITE_TEST_PACKET_TYPE"),
+            )
         )
+
         fsm.act("TRANSMIT",
             self.source.stb.eq(1),
             If(self.source.ack,
@@ -230,35 +233,11 @@ class TX_Command_Packet(Module, AutoCSR):
             ),
             If(addr_next == self.tx_word_len.storage,
                 self.source.eop.eq(1),
-                tx_done.eq(1),
                 NextState("IDLE")
             )
         )
 
-class TX_Test_Packet(Module, AutoCSR):
-    def __init__(self):
-        self.tx = CSR()
-
-        # # #
-        
-        tx_done = Signal()
-        self.sync += [
-            If(self.tx.re, self.tx.w.eq(1)),
-            If(tx_done, self.tx.w.eq(0)),
-        ]
-
-        self.source = stream.Endpoint(word_layout)
-        self.submodules.fsm = fsm = FSM(reset_state="IDLE")
-        
-        cnt = Signal(max=0xFFF)
-        fsm.act("IDLE",
-            NextValue(cnt, cnt.reset),
-            If(self.tx.re,
-               NextState("WRITE_PACKET_TYPE")
-            )
-        )
-
-        fsm.act("WRITE_PACKET_TYPE",
+        fsm.act("WRITE_TEST_PACKET_TYPE",
             self.source.stb.eq(1),
             self.source.data.eq(Replicate(C(0x04, char_width), 4)),
             self.source.k.eq(0b0000),
@@ -271,7 +250,6 @@ class TX_Test_Packet(Module, AutoCSR):
             self.source.k.eq(0b0000),
             If(self.source.ack,
                 If(cnt == 0xFFF-3,
-                    tx_done.eq(1),
                     self.source.eop.eq(1),
                     NextState("IDLE")
                 ).Else(
@@ -281,8 +259,6 @@ class TX_Test_Packet(Module, AutoCSR):
             )
         )
 
-
-
 class RX_Debug_Buffer(Module,AutoCSR):
     def __init__(self):
         self.submodules.buf_out = buf_out = stream.SyncFIFO(word_layout, 128)
@@ -302,26 +278,24 @@ class RX_Debug_Buffer(Module,AutoCSR):
         ]
 
 class Duplicate_Majority_Voter(Module):
-    def __init__(self, data, k):
-        assert data.nbits == 32
-        assert k.nbits == 4
+    def __init__(self, char_4x, k_4x):
+        assert char_4x.nbits == 32
+        assert k_4x.nbits == 4
         
         # Section 9.2.2.1 (CXP-001-2021)
         # decoder should immune to single bit errors when handling duplicated characters
         self.char = Signal(char_width)
         self.k = Signal()
 
-        a, a_k = data[:8], k[0]
-        b, b_k = data[8:16], k[1]
-        c, c_k = data[16:24], k[2]
-        d, d_k = data[24:], k[3]
+        a, b, c, d = [char_4x[i*8:(i+1)*8] for i in range(4)]
+        a_k, b_k, c_k, d_k = [k_4x[i:(i+1)] for i in range(4)]
         self.comb += [
             self.char.eq(a&b&c | a&b&d | a&c&d | b&c&d),
             self.k.eq(a_k&b_k&c_k | a_k&b_k&d_k | a_k&c_k&d_k | b_k&c_k&d_k),
         ]
 
 @FullMemoryWE()
-class CXP_Data_Packet_Decode(Module):
+class RX_Bootstrap(Module):
     def __init__(self):
         self.packet_type = Signal(8)
 

src/gateware/zc706.py

@@ -718,19 +718,17 @@ class CXP_FMC():
             self.csr_devices.append(cxp_name)
             cxp_csr_group.append(cxp_name)
             
+            rx_mem_name = "cxp_rx" + str(i) + "_mem"
+            rx_mem_size = cxp_interface.get_rx_mem_size()
+            cxp_rx_mem_group.append(rx_mem_name)
+            memory_address = self.axi2csr.register_port(cxp_interface.get_rx_port(), rx_mem_size)
+            self.add_memory_region(rx_mem_name, self.mem_map["csr"] + memory_address, rx_mem_size)
 
             tx_mem_name = "cxp_tx" + str(i) + "_mem"
             tx_mem_size = cxp_interface.get_tx_mem_size()
+            cxp_tx_mem_group.append(tx_mem_name)
             memory_address = self.axi2csr.register_port(cxp_interface.get_tx_port(), tx_mem_size)
             self.add_memory_region(tx_mem_name, self.mem_map["csr"] + memory_address, tx_mem_size)
-            cxp_tx_mem_group.append(tx_mem_name)
-
-            rx_mem_name = "cxp_rx" + str(i) + "_mem"
-            rx_mem_size = cxp_interface.get_rx_mem_size()
-            memory_address = self.axi2csr.register_port(cxp_interface.get_rx_port(), rx_mem_size)
-            self.add_memory_region(rx_mem_name, self.mem_map["csr"] + memory_address, rx_mem_size)
-            cxp_rx_mem_group.append(rx_mem_name)
-
 
             # DEBUG loopback tx memory
             loopback_mem_name = "cxp_loopback_tx" + str(i) + "_mem"

src/libboard_artiq/src/cxp_downconn.rs

@@ -2,25 +2,11 @@ use embedded_hal::prelude::_embedded_hal_blocking_delay_DelayUs;
 use libboard_zynq::{println, timer::GlobalTimer};
 use log::info;
 
-// use log::info;
-use crate::{cxp_proto,
-            pl::{csr, csr::CXP}};
+use crate::{cxp_phys, cxp_proto, pl::csr::CXP};
 
-#[derive(Clone, Copy, Debug)]
-#[allow(non_camel_case_types)]
-pub enum CXP_SPEED {
-    CXP_1,
-    CXP_2,
-    CXP_3,
-    CXP_5,
-    CXP_6,
-    CXP_10,
-    CXP_12,
-}
-
-pub fn loopback_testing(channel: usize, timer: &mut GlobalTimer, speed: CXP_SPEED) {
+pub fn loopback_testing(channel: usize, timer: &mut GlobalTimer, speed: cxp_phys::CXP_SPEED) {
     println!("==============================================================================");
-    cxp_gtx::change_linerate(channel, timer, speed);
+    cxp_phys::change_linerate(channel, timer, speed);
 
     unsafe {
         info!("waiting for tx&rx setup...");
@@ -71,8 +57,11 @@ pub fn loopback_testing(channel: usize, timer: &mut GlobalTimer, speed: CXP_SPEE
         (CXP[channel].downconn_trigger_ack_write)(1);
         info!("after clr trig ack = {}", (CXP[channel].downconn_trigger_ack_read)());
 
-        info!("decoder error = {}", (CXP[channel].downconn_decoder_error_read)());
-        info!("test error = {}", (CXP[channel].downconn_test_error_read)());
+        info!(
+            "decoder error = {}",
+            (CXP[channel].downconn_bootstrap_decoder_err_read)()
+        );
+        info!("test error = {}", (CXP[channel].downconn_bootstrap_test_err_read)());
         info!("packet type = {:#06X}", (CXP[channel].downconn_packet_type_read)());
 
         cxp_proto::receive(channel).expect("loopback gtx rx error");
@@ -96,439 +85,3 @@ pub fn loopback_testing(channel: usize, timer: &mut GlobalTimer, speed: CXP_SPEE
         cxp_proto::print_packetu32(&pak_arr, &k_arr);
     }
 }
-
-pub fn setup(timer: &mut GlobalTimer) {
-    // TODO: do a for loop for channel?
-    let channel: usize = 0;
-    unsafe {
-        info!("turning on pmc loopback mode...");
-        (CXP[channel].downconn_loopback_mode_write)(0b010); // Near-End PMA Loopback
-
-        // QPLL setup
-        csr::cxp_phys::downconn_qpll_reset_write(1);
-        info!("waiting for QPLL/CPLL to lock...");
-        while csr::cxp_phys::downconn_qpll_locked_read() != 1 {}
-        info!("QPLL locked");
-
-        // tx/rx setup
-        (CXP[channel].downconn_tx_start_init_write)(1);
-        (CXP[channel].downconn_rx_start_init_write)(1);
-
-        info!("waiting for tx & rx setup...");
-        timer.delay_us(50_000);
-        info!(
-            "tx_phaligndone = {} | rx_phaligndone = {}",
-            (CXP[channel].downconn_txinit_phaligndone_read)(),
-            (CXP[channel].downconn_rxinit_phaligndone_read)(),
-        );
-    }
-
-    cxp_gtx::change_linerate(channel, timer, CXP_SPEED::CXP_1);
-}
-
-pub mod cxp_gtx {
-    use super::*;
-
-    struct CdrConfig {
-        pub cfg_reg0: u16, // addr = 0xA8
-        pub cfg_reg1: u16, // addr = 0xA9
-        pub cfg_reg2: u16, // addr = 0xAA
-        pub cfg_reg3: u16, // addr = 0xAB
-        pub cfg_reg4: u16, // addr = 0xAC
-    }
-
-    pub fn change_linerate(channel: usize, timer: &mut GlobalTimer, speed: CXP_SPEED) {
-        info!("Changing datarate to {:?}", speed);
-        // DEBUG: DRP pll for TXUSRCLK = freq(linerate)/20
-        let settings = txusrclk::get_txusrclk_config(speed);
-        txusrclk::setup(channel, timer, settings);
-
-        change_qpll_fb_divider(speed);
-        change_gtx_divider(channel, speed);
-        change_cdr_cfg(channel, speed);
-
-        unsafe {
-            csr::cxp_phys::downconn_qpll_reset_write(1);
-            info!("waiting for QPLL/CPLL to lock...");
-            while csr::cxp_phys::downconn_qpll_locked_read() != 1 {}
-            info!("QPLL locked");
-        }
-
-        unsafe {
-            (CXP[channel].downconn_tx_restart_write)(1);
-            (CXP[channel].downconn_rx_restart_write)(1);
-        }
-    }
-
-    fn change_qpll_fb_divider(speed: CXP_SPEED) {
-        let qpll_div_reg = match speed {
-            CXP_SPEED::CXP_1 | CXP_SPEED::CXP_2 | CXP_SPEED::CXP_5 | CXP_SPEED::CXP_10 => 0x0120, // FB_Divider = 80
-            CXP_SPEED::CXP_3 | CXP_SPEED::CXP_6 | CXP_SPEED::CXP_12 => 0x0170,                    // FB_Divider = 100
-        };
-
-        println!("0x36 = {:#06x}", qpll_read(0x36));
-        qpll_write(0x36, qpll_div_reg);
-        println!("0x36 = {:#06x}", qpll_read(0x36));
-    }
-
-    fn change_gtx_divider(channel: usize, speed: CXP_SPEED) {
-        let div_reg = match speed {
-            CXP_SPEED::CXP_1 => 0x33,                      // RXOUT_DIV = 8
-            CXP_SPEED::CXP_2 | CXP_SPEED::CXP_3 => 0x22,   // RXOUT_DIV = 4
-            CXP_SPEED::CXP_5 | CXP_SPEED::CXP_6 => 0x11,   // RXOUT_DIV = 2
-            CXP_SPEED::CXP_10 | CXP_SPEED::CXP_12 => 0x00, // RXOUT_DIV = 1
-        };
-
-        println!("0x88 = {:#06x}", gtx_read(channel, 0x88));
-        gtx_write(channel, 0x88, div_reg);
-        println!("0x88 = {:#06x}", gtx_read(channel, 0x88));
-    }
-
-    fn change_cdr_cfg(channel: usize, speed: CXP_SPEED) {
-        let cdr_cfg = match speed {
-            // when RXOUT_DIV = 8
-            CXP_SPEED::CXP_1 => {
-                CdrConfig {
-                    cfg_reg0: 0x0020, //0x0A8
-                    cfg_reg1: 0x1008, //0x0A9
-                    cfg_reg2: 0x23FF, //0x0AA
-                    cfg_reg3: 0x0000, //0x0AB
-                    cfg_reg4: 0x0003, //0x0AC
-                }
-            }
-            // when RXOUT_DIV = 4
-            CXP_SPEED::CXP_2 | CXP_SPEED::CXP_5 => {
-                CdrConfig {
-                    cfg_reg0: 0x0020, //0x0A8
-                    cfg_reg1: 0x1010, //0x0A9
-                    cfg_reg2: 0x23FF, //0x0AA
-                    cfg_reg3: 0x0000, //0x0AB
-                    cfg_reg4: 0x0003, //0x0AC
-                }
-            }
-            // when RXOUT_DIV= 2
-            CXP_SPEED::CXP_3 | CXP_SPEED::CXP_6 => {
-                CdrConfig {
-                    cfg_reg0: 0x0020, //0x0A8
-                    cfg_reg1: 0x1020, //0x0A9
-                    cfg_reg2: 0x23FF, //0x0AA
-                    cfg_reg3: 0x0000, //0x0AB
-                    cfg_reg4: 0x0003, //0x0AC
-                }
-            }
-            // when RXOUT_DIV= 1
-            CXP_SPEED::CXP_10 | CXP_SPEED::CXP_12 => {
-                CdrConfig {
-                    cfg_reg0: 0x0020, //0x0A8
-                    cfg_reg1: 0x1040, //0x0A9
-                    cfg_reg2: 0x23FF, //0x0AA
-                    cfg_reg3: 0x0000, //0x0AB
-                    cfg_reg4: 0x000B, //0x0AC
-                }
-            }
-        };
-
-        gtx_write(channel, 0x0A8, cdr_cfg.cfg_reg0);
-        gtx_write(channel, 0x0A9, cdr_cfg.cfg_reg1);
-        gtx_write(channel, 0x0AA, cdr_cfg.cfg_reg2);
-        gtx_write(channel, 0x0AB, cdr_cfg.cfg_reg3);
-        gtx_write(channel, 0x0AC, cdr_cfg.cfg_reg4);
-    }
-
-    #[allow(dead_code)]
-    fn gtx_read(channel: usize, address: u16) -> u16 {
-        unsafe {
-            (CXP[channel].downconn_gtx_daddr_write)(address);
-            (CXP[channel].downconn_gtx_dread_write)(1);
-            while (CXP[channel].downconn_gtx_dready_read)() != 1 {}
-            (CXP[channel].downconn_gtx_dout_read)()
-        }
-    }
-
-    fn gtx_write(channel: usize, address: u16, value: u16) {
-        unsafe {
-            (CXP[channel].downconn_gtx_daddr_write)(address);
-            (CXP[channel].downconn_gtx_din_write)(value);
-            (CXP[channel].downconn_gtx_din_stb_write)(1);
-            while (CXP[channel].downconn_gtx_dready_read)() != 1 {}
-        }
-    }
-
-    #[allow(dead_code)]
-    fn qpll_read(address: u8) -> u16 {
-        unsafe {
-            csr::cxp_phys::downconn_qpll_daddr_write(address);
-            csr::cxp_phys::downconn_qpll_dread_write(1);
-            while csr::cxp_phys::downconn_qpll_dready_read() != 1 {}
-            csr::cxp_phys::downconn_qpll_dout_read()
-        }
-    }
-
-    fn qpll_write(address: u8, value: u16) {
-        unsafe {
-            csr::cxp_phys::downconn_qpll_daddr_write(address);
-            csr::cxp_phys::downconn_qpll_din_write(value);
-            csr::cxp_phys::downconn_qpll_din_stb_write(1);
-            while csr::cxp_phys::downconn_qpll_dready_read() != 1 {}
-        }
-    }
-}
-
-pub mod txusrclk {
-    use super::*;
-
-    pub struct PLLSetting {
-        pub clkout0_reg1: u16,  //0x08
-        pub clkout0_reg2: u16,  //0x09
-        pub clkfbout_reg1: u16, //0x14
-        pub clkfbout_reg2: u16, //0x15
-        pub div_reg: u16,       //0x16
-        pub lock_reg1: u16,     //0x18
-        pub lock_reg2: u16,     //0x19
-        pub lock_reg3: u16,     //0x1A
-        pub power_reg: u16,     //0x28
-        pub filt_reg1: u16,     //0x4E
-        pub filt_reg2: u16,     //0x4F
-    }
-
-    fn one_clock_cycle(channel: usize) {
-        unsafe {
-            (CXP[channel].downconn_pll_dclk_write)(1);
-            (CXP[channel].downconn_pll_dclk_write)(0);
-        }
-    }
-
-    fn set_addr(channel: usize, address: u8) {
-        unsafe {
-            (CXP[channel].downconn_pll_daddr_write)(address);
-        }
-    }
-
-    fn set_data(channel: usize, value: u16) {
-        unsafe {
-            (CXP[channel].downconn_pll_din_write)(value);
-        }
-    }
-
-    fn set_enable(channel: usize, en: bool) {
-        unsafe {
-            let val = if en { 1 } else { 0 };
-            (CXP[channel].downconn_pll_den_write)(val);
-        }
-    }
-
-    fn set_write_enable(channel: usize, en: bool) {
-        unsafe {
-            let val = if en { 1 } else { 0 };
-            (CXP[channel].downconn_pll_dwen_write)(val);
-        }
-    }
-
-    fn get_data(channel: usize) -> u16 {
-        unsafe { (CXP[channel].downconn_pll_dout_read)() }
-    }
-
-    fn drp_ready(channel: usize) -> bool {
-        unsafe { (CXP[channel].downconn_pll_dready_read)() == 1 }
-    }
-
-    #[allow(dead_code)]
-    fn read(channel: usize, address: u8) -> u16 {
-        set_addr(channel, address);
-        set_enable(channel, true);
-        // Set DADDR on the mmcm and assert DEN for one clock cycle
-        one_clock_cycle(channel);
-
-        set_enable(channel, false);
-        while !drp_ready(channel) {
-            // keep the clock signal until data is ready
-            one_clock_cycle(channel);
-        }
-        get_data(channel)
-    }
-
-    fn write(channel: usize, address: u8, value: u16) {
-        set_addr(channel, address);
-        set_data(channel, value);
-        set_write_enable(channel, true);
-        set_enable(channel, true);
-        // Set DADDR, DI on the mmcm and assert DWE, DEN for one clock cycle
-        one_clock_cycle(channel);
-
-        set_write_enable(channel, false);
-        set_enable(channel, false);
-        while !drp_ready(channel) {
-            // keep the clock signal until write is finished
-            one_clock_cycle(channel);
-        }
-    }
-
-    fn reset(channel: usize, rst: bool) {
-        unsafe {
-            let val = if rst { 1 } else { 0 };
-            (CXP[channel].downconn_txpll_reset_write)(val)
-        }
-    }
-
-    pub fn setup(channel: usize, timer: &mut GlobalTimer, settings: PLLSetting) {
-        if false {
-            info!("0x08 = {:#06x}", read(channel, 0x08));
-            info!("0x09 = {:#06x}", read(channel, 0x09));
-            info!("0x14 = {:#06x}", read(channel, 0x14));
-            info!("0x15 = {:#06x}", read(channel, 0x15));
-            info!("0x16 = {:#06x}", read(channel, 0x16));
-            info!("0x18 = {:#06x}", read(channel, 0x18));
-            info!("0x19 = {:#06x}", read(channel, 0x19));
-            info!("0x1A = {:#06x}", read(channel, 0x1A));
-            info!("0x28 = {:#06x}", read(channel, 0x28));
-            info!("0x4E = {:#06x}", read(channel, 0x4E));
-            info!("0x4F = {:#06x}", read(channel, 0x4F));
-        } else {
-            // Based on "DRP State Machine" from XAPP888
-            // hold reset HIGH during pll config
-            reset(channel, true);
-            write(channel, 0x08, settings.clkout0_reg1);
-            write(channel, 0x09, settings.clkout0_reg2);
-            write(channel, 0x14, settings.clkfbout_reg1);
-            write(channel, 0x15, settings.clkfbout_reg2);
-            write(channel, 0x16, settings.div_reg);
-            write(channel, 0x18, settings.lock_reg1);
-            write(channel, 0x19, settings.lock_reg2);
-            write(channel, 0x1A, settings.lock_reg3);
-            write(channel, 0x28, settings.power_reg);
-            write(channel, 0x4E, settings.filt_reg1);
-            write(channel, 0x4F, settings.filt_reg2);
-            reset(channel, false);
-
-            // wait for the pll to lock
-            timer.delay_us(100);
-
-            let locked = unsafe { (CXP[channel].downconn_txpll_locked_read)() == 1 };
-            info!("txusrclk locked = {}", locked);
-        }
-    }
-
-    pub fn get_txusrclk_config(speed: CXP_SPEED) -> PLLSetting {
-        match speed {
-            CXP_SPEED::CXP_1 => {
-                // CLKFBOUT_MULT = 8, DIVCLK_DIVIDE = 1 , CLKOUT0_DIVIDE = 32
-                // TXUSRCLK=62.5MHz
-                PLLSetting {
-                    clkout0_reg1: 0x1410,  //0x08
-                    clkout0_reg2: 0x0000,  //0x09
-                    clkfbout_reg1: 0x1104, //0x14
-                    clkfbout_reg2: 0x0000, //0x15
-                    div_reg: 0x1041,       //0x16
-                    lock_reg1: 0x03e8,     //0x18
-                    lock_reg2: 0x5801,     //0x19
-                    lock_reg3: 0xdbe9,     //0x1A
-                    power_reg: 0x0000,     //0x28
-                    filt_reg1: 0x9808,     //0x4E
-                    filt_reg2: 0x9100,     //0x4F
-                }
-            }
-            CXP_SPEED::CXP_2 => {
-                // CLKFBOUT_MULT = 8, DIVCLK_DIVIDE = 1 , CLKOUT0_DIVIDE = 16
-                // TXUSRCLK=62.5MHz
-                PLLSetting {
-                    clkout0_reg1: 0x1208,  //0x08
-                    clkout0_reg2: 0x0000,  //0x09
-                    clkfbout_reg1: 0x1104, //0x14
-                    clkfbout_reg2: 0x0000, //0x15
-                    div_reg: 0x1041,       //0x16
-                    lock_reg1: 0x03e8,     //0x18
-                    lock_reg2: 0x5801,     //0x19
-                    lock_reg3: 0xdbe9,     //0x1A
-                    power_reg: 0x0000,     //0x28
-                    filt_reg1: 0x9808,     //0x4E
-                    filt_reg2: 0x9100,     //0x4F
-                }
-            }
-            CXP_SPEED::CXP_3 => {
-                // CLKFBOUT_MULT = 10, DIVCLK_DIVIDE = 1 , CLKOUT0_DIVIDE = 16
-                // TXUSRCLK=78.125MHz
-                PLLSetting {
-                    clkout0_reg1: 0x1208,  //0x08
-                    clkout0_reg2: 0x0000,  //0x09
-                    clkfbout_reg1: 0x1145, //0x14
-                    clkfbout_reg2: 0x0000, //0x15
-                    div_reg: 0x1041,       //0x16
-                    lock_reg1: 0x03e8,     //0x18
-                    lock_reg2: 0x7001,     //0x19
-                    lock_reg3: 0xf3e9,     //0x1A
-                    power_reg: 0x0000,     //0x28
-                    filt_reg1: 0x9908,     //0x4E
-                    filt_reg2: 0x1900,     //0x4F
-                }
-            }
-            CXP_SPEED::CXP_5 => {
-                // CLKFBOUT_MULT = 8, DIVCLK_DIVIDE = 1 , CLKOUT0_DIVIDE = 8
-                // TXUSRCLK=125MHz
-                PLLSetting {
-                    clkout0_reg1: 0x1104,  //0x08
-                    clkout0_reg2: 0x0000,  //0x09
-                    clkfbout_reg1: 0x1104, //0x14
-                    clkfbout_reg2: 0x0000, //0x15
-                    div_reg: 0x1041,       //0x16
-                    lock_reg1: 0x03e8,     //0x18
-                    lock_reg2: 0x5801,     //0x19
-                    lock_reg3: 0xdbe9,     //0x1A
-                    power_reg: 0x0000,     //0x28
-                    filt_reg1: 0x9808,     //0x4E
-                    filt_reg2: 0x9100,     //0x4F
-                }
-            }
-            CXP_SPEED::CXP_6 => {
-                // CLKFBOUT_MULT = 10, DIVCLK_DIVIDE = 1 , CLKOUT0_DIVIDE = 8
-                // TXUSRCLK=156.25MHz
-                PLLSetting {
-                    clkout0_reg1: 0x1104,  //0x08
-                    clkout0_reg2: 0x0000,  //0x09
-                    clkfbout_reg1: 0x1145, //0x14
-                    clkfbout_reg2: 0x0000, //0x15
-                    div_reg: 0x1041,       //0x16
-                    lock_reg1: 0x03e8,     //0x18
-                    lock_reg2: 0x7001,     //0x19
-                    lock_reg3: 0xf3e9,     //0x1A
-                    power_reg: 0x0000,     //0x28
-                    filt_reg1: 0x9908,     //0x4E
-                    filt_reg2: 0x1900,     //0x4F
-                }
-            }
-            CXP_SPEED::CXP_10 => {
-                // CLKFBOUT_MULT = 8, DIVCLK_DIVIDE = 1 , CLKOUT0_DIVIDE = 4
-                // TXUSRCLK=250MHz
-                PLLSetting {
-                    clkout0_reg1: 0x1082,  //0x08
-                    clkout0_reg2: 0x0000,  //0x09
-                    clkfbout_reg1: 0x1104, //0x14
-                    clkfbout_reg2: 0x0000, //0x15
-                    div_reg: 0x1041,       //0x16
-                    lock_reg1: 0x03e8,     //0x18
-                    lock_reg2: 0x5801,     //0x19
-                    lock_reg3: 0xdbe9,     //0x1A
-                    power_reg: 0x0000,     //0x28
-                    filt_reg1: 0x9808,     //0x4E
-                    filt_reg2: 0x9100,     //0x4F
-                }
-            }
-            CXP_SPEED::CXP_12 => {
-                // CLKFBOUT_MULT = 10, DIVCLK_DIVIDE = 1 , CLKOUT0_DIVIDE = 4
-                // TXUSRCLK=312.5MHz
-                PLLSetting {
-                    clkout0_reg1: 0x1082,  //0x08
-                    clkout0_reg2: 0x0000,  //0x09
-                    clkfbout_reg1: 0x1145, //0x14
-                    clkfbout_reg2: 0x0000, //0x15
-                    div_reg: 0x1041,       //0x16
-                    lock_reg1: 0x03e8,     //0x18
-                    lock_reg2: 0x7001,     //0x19
-                    lock_reg3: 0xf3e9,     //0x1A
-                    power_reg: 0x0000,     //0x28
-                    filt_reg1: 0x9908,     //0x4E
-                    filt_reg2: 0x1900,     //0x4F
-                }
-            }
-        }
-    }
-}

src/libboard_artiq/src/cxp_phys.rs

@@ -0,0 +1,482 @@
+use embedded_hal::prelude::_embedded_hal_blocking_delay_DelayUs;
+use libboard_zynq::{println, timer::GlobalTimer};
+use log::info;
+
+use crate::pl::{csr, csr::CXP};
+
+#[derive(Clone, Copy, Debug)]
+#[allow(non_camel_case_types)]
+pub enum CXP_SPEED {
+    CXP_1,
+    CXP_2,
+    CXP_3,
+    CXP_5,
+    CXP_6,
+    CXP_10,
+    CXP_12,
+}
+
+pub fn setup(timer: &mut GlobalTimer) {
+    down_conn::setup(timer);
+    up_conn::setup();
+}
+
+pub fn change_linerate(channel: usize, timer: &mut GlobalTimer, speed: CXP_SPEED) {
+    info!("Changing channel {}'s datarate to {:?}", channel, speed);
+    down_conn::change_linerate(channel, timer, speed);
+    up_conn::change_linerate(channel, speed);
+}
+
+mod up_conn {
+    use super::*;
+
+    pub fn setup() {
+        // TODO: do a for loop for channel?
+        let channel: usize = 0;
+        unsafe {
+            change_linerate(channel, CXP_SPEED::CXP_1);
+            (CXP[channel].upconn_tx_enable_write)(1);
+        }
+    }
+
+    pub fn change_linerate(channel: usize, speed: CXP_SPEED) {
+        unsafe {
+            (CXP[channel].upconn_clk_reset_write)(1);
+            match speed {
+                CXP_SPEED::CXP_10 | CXP_SPEED::CXP_12 => {
+                    (CXP[channel].upconn_bitrate2x_enable_write)(1);
+                }
+                _ => {}
+            };
+            (CXP[channel].upconn_clk_reset_write)(0);
+        }
+    }
+}
+
+mod down_conn {
+    use super::*;
+
+    pub fn setup(timer: &mut GlobalTimer) {
+        // TODO: do a for loop for channel?
+        let channel: usize = 0;
+        unsafe {
+            info!("turning on pmc loopback mode...");
+            (CXP[channel].downconn_loopback_mode_write)(0b010); // Near-End PMA Loopback
+
+            // QPLL setup
+            csr::cxp_phys::downconn_qpll_reset_write(1);
+            info!("waiting for QPLL/CPLL to lock...");
+            while csr::cxp_phys::downconn_qpll_locked_read() != 1 {}
+            info!("QPLL locked");
+
+            // tx/rx setup
+            (CXP[channel].downconn_tx_start_init_write)(1);
+            (CXP[channel].downconn_rx_start_init_write)(1);
+
+            info!("waiting for tx & rx setup...");
+            timer.delay_us(50_000);
+            info!(
+                "tx_phaligndone = {} | rx_phaligndone = {}",
+                (CXP[channel].downconn_txinit_phaligndone_read)(),
+                (CXP[channel].downconn_rxinit_phaligndone_read)(),
+            );
+        }
+
+        change_linerate(channel, timer, CXP_SPEED::CXP_1);
+    }
+
+    pub fn change_linerate(channel: usize, timer: &mut GlobalTimer, speed: CXP_SPEED) {
+        // DEBUG: DRP pll for TXUSRCLK = freq(linerate)/20
+        let settings = txusrclk::get_txusrclk_config(speed);
+        txusrclk::setup(channel, timer, settings);
+
+        change_qpll_fb_divider(speed);
+        change_gtx_divider(channel, speed);
+        change_cdr_cfg(channel, speed);
+
+        unsafe {
+            csr::cxp_phys::downconn_qpll_reset_write(1);
+            info!("waiting for QPLL/CPLL to lock...");
+            while csr::cxp_phys::downconn_qpll_locked_read() != 1 {}
+            info!("QPLL locked");
+        }
+
+        unsafe {
+            (CXP[channel].downconn_tx_restart_write)(1);
+            (CXP[channel].downconn_rx_restart_write)(1);
+        }
+    }
+
+    fn change_qpll_fb_divider(speed: CXP_SPEED) {
+        let qpll_div_reg = match speed {
+            CXP_SPEED::CXP_1 | CXP_SPEED::CXP_2 | CXP_SPEED::CXP_5 | CXP_SPEED::CXP_10 => 0x0120, // FB_Divider = 80
+            CXP_SPEED::CXP_3 | CXP_SPEED::CXP_6 | CXP_SPEED::CXP_12 => 0x0170,                    // FB_Divider = 100
+        };
+
+        println!("0x36 = {:#06x}", qpll_read(0x36));
+        qpll_write(0x36, qpll_div_reg);
+        println!("0x36 = {:#06x}", qpll_read(0x36));
+    }
+
+    fn change_gtx_divider(channel: usize, speed: CXP_SPEED) {
+        let div_reg = match speed {
+            CXP_SPEED::CXP_1 => 0x33,                      // RXOUT_DIV = 8
+            CXP_SPEED::CXP_2 | CXP_SPEED::CXP_3 => 0x22,   // RXOUT_DIV = 4
+            CXP_SPEED::CXP_5 | CXP_SPEED::CXP_6 => 0x11,   // RXOUT_DIV = 2
+            CXP_SPEED::CXP_10 | CXP_SPEED::CXP_12 => 0x00, // RXOUT_DIV = 1
+        };
+
+        println!("0x88 = {:#06x}", gtx_read(channel, 0x88));
+        gtx_write(channel, 0x88, div_reg);
+        println!("0x88 = {:#06x}", gtx_read(channel, 0x88));
+    }
+
+    fn change_cdr_cfg(channel: usize, speed: CXP_SPEED) {
+        struct CdrConfig {
+            pub cfg_reg0: u16, // addr = 0xA8
+            pub cfg_reg1: u16, // addr = 0xA9
+            pub cfg_reg2: u16, // addr = 0xAA
+            pub cfg_reg3: u16, // addr = 0xAB
+            pub cfg_reg4: u16, // addr = 0xAC
+        }
+
+        let cdr_cfg = match speed {
+            // when RXOUT_DIV = 8
+            CXP_SPEED::CXP_1 => CdrConfig {
+                cfg_reg0: 0x0020,
+                cfg_reg1: 0x1008,
+                cfg_reg2: 0x23FF,
+                cfg_reg3: 0x0000,
+                cfg_reg4: 0x0003,
+            },
+            // when RXOUT_DIV = 4
+            CXP_SPEED::CXP_2 | CXP_SPEED::CXP_5 => CdrConfig {
+                cfg_reg0: 0x0020,
+                cfg_reg1: 0x1010,
+                cfg_reg2: 0x23FF,
+                cfg_reg3: 0x0000,
+                cfg_reg4: 0x0003,
+            },
+            // when RXOUT_DIV= 2
+            CXP_SPEED::CXP_3 | CXP_SPEED::CXP_6 => CdrConfig {
+                cfg_reg0: 0x0020,
+                cfg_reg1: 0x1020,
+                cfg_reg2: 0x23FF,
+                cfg_reg3: 0x0000,
+                cfg_reg4: 0x0003,
+            },
+            // when RXOUT_DIV= 1
+            CXP_SPEED::CXP_10 | CXP_SPEED::CXP_12 => CdrConfig {
+                cfg_reg0: 0x0020,
+                cfg_reg1: 0x1040,
+                cfg_reg2: 0x23FF,
+                cfg_reg3: 0x0000,
+                cfg_reg4: 0x000B,
+            },
+        };
+
+        gtx_write(channel, 0x0A8, cdr_cfg.cfg_reg0);
+        gtx_write(channel, 0x0A9, cdr_cfg.cfg_reg1);
+        gtx_write(channel, 0x0AA, cdr_cfg.cfg_reg2);
+        gtx_write(channel, 0x0AB, cdr_cfg.cfg_reg3);
+        gtx_write(channel, 0x0AC, cdr_cfg.cfg_reg4);
+    }
+
+    #[allow(dead_code)]
+    fn gtx_read(channel: usize, address: u16) -> u16 {
+        unsafe {
+            (CXP[channel].downconn_gtx_daddr_write)(address);
+            (CXP[channel].downconn_gtx_dread_write)(1);
+            while (CXP[channel].downconn_gtx_dready_read)() != 1 {}
+            (CXP[channel].downconn_gtx_dout_read)()
+        }
+    }
+
+    fn gtx_write(channel: usize, address: u16, value: u16) {
+        unsafe {
+            (CXP[channel].downconn_gtx_daddr_write)(address);
+            (CXP[channel].downconn_gtx_din_write)(value);
+            (CXP[channel].downconn_gtx_din_stb_write)(1);
+            while (CXP[channel].downconn_gtx_dready_read)() != 1 {}
+        }
+    }
+
+    #[allow(dead_code)]
+    fn qpll_read(address: u8) -> u16 {
+        unsafe {
+            csr::cxp_phys::downconn_qpll_daddr_write(address);
+            csr::cxp_phys::downconn_qpll_dread_write(1);
+            while csr::cxp_phys::downconn_qpll_dready_read() != 1 {}
+            csr::cxp_phys::downconn_qpll_dout_read()
+        }
+    }
+
+    fn qpll_write(address: u8, value: u16) {
+        unsafe {
+            csr::cxp_phys::downconn_qpll_daddr_write(address);
+            csr::cxp_phys::downconn_qpll_din_write(value);
+            csr::cxp_phys::downconn_qpll_din_stb_write(1);
+            while csr::cxp_phys::downconn_qpll_dready_read() != 1 {}
+        }
+    }
+
+    // DEBUG: remove this
+    pub mod txusrclk {
+        use super::*;
+
+        pub struct PLLSetting {
+            pub clkout0_reg1: u16,  //0x08
+            pub clkout0_reg2: u16,  //0x09
+            pub clkfbout_reg1: u16, //0x14
+            pub clkfbout_reg2: u16, //0x15
+            pub div_reg: u16,       //0x16
+            pub lock_reg1: u16,     //0x18
+            pub lock_reg2: u16,     //0x19
+            pub lock_reg3: u16,     //0x1A
+            pub power_reg: u16,     //0x28
+            pub filt_reg1: u16,     //0x4E
+            pub filt_reg2: u16,     //0x4F
+        }
+
+        fn one_clock_cycle(channel: usize) {
+            unsafe {
+                (CXP[channel].downconn_pll_dclk_write)(1);
+                (CXP[channel].downconn_pll_dclk_write)(0);
+            }
+        }
+
+        fn set_addr(channel: usize, address: u8) {
+            unsafe {
+                (CXP[channel].downconn_pll_daddr_write)(address);
+            }
+        }
+
+        fn set_data(channel: usize, value: u16) {
+            unsafe {
+                (CXP[channel].downconn_pll_din_write)(value);
+            }
+        }
+
+        fn set_enable(channel: usize, en: bool) {
+            unsafe {
+                let val = if en { 1 } else { 0 };
+                (CXP[channel].downconn_pll_den_write)(val);
+            }
+        }
+
+        fn set_write_enable(channel: usize, en: bool) {
+            unsafe {
+                let val = if en { 1 } else { 0 };
+                (CXP[channel].downconn_pll_dwen_write)(val);
+            }
+        }
+
+        fn get_data(channel: usize) -> u16 {
+            unsafe { (CXP[channel].downconn_pll_dout_read)() }
+        }
+
+        fn drp_ready(channel: usize) -> bool {
+            unsafe { (CXP[channel].downconn_pll_dready_read)() == 1 }
+        }
+
+        #[allow(dead_code)]
+        fn read(channel: usize, address: u8) -> u16 {
+            set_addr(channel, address);
+            set_enable(channel, true);
+            // Set DADDR on the mmcm and assert DEN for one clock cycle
+            one_clock_cycle(channel);
+
+            set_enable(channel, false);
+            while !drp_ready(channel) {
+                // keep the clock signal until data is ready
+                one_clock_cycle(channel);
+            }
+            get_data(channel)
+        }
+
+        fn write(channel: usize, address: u8, value: u16) {
+            set_addr(channel, address);
+            set_data(channel, value);
+            set_write_enable(channel, true);
+            set_enable(channel, true);
+            // Set DADDR, DI on the mmcm and assert DWE, DEN for one clock cycle
+            one_clock_cycle(channel);
+
+            set_write_enable(channel, false);
+            set_enable(channel, false);
+            while !drp_ready(channel) {
+                // keep the clock signal until write is finished
+                one_clock_cycle(channel);
+            }
+        }
+
+        fn reset(channel: usize, rst: bool) {
+            unsafe {
+                let val = if rst { 1 } else { 0 };
+                (CXP[channel].downconn_txpll_reset_write)(val)
+            }
+        }
+
+        pub fn setup(channel: usize, timer: &mut GlobalTimer, settings: PLLSetting) {
+            if false {
+                info!("0x08 = {:#06x}", read(channel, 0x08));
+                info!("0x09 = {:#06x}", read(channel, 0x09));
+                info!("0x14 = {:#06x}", read(channel, 0x14));
+                info!("0x15 = {:#06x}", read(channel, 0x15));
+                info!("0x16 = {:#06x}", read(channel, 0x16));
+                info!("0x18 = {:#06x}", read(channel, 0x18));
+                info!("0x19 = {:#06x}", read(channel, 0x19));
+                info!("0x1A = {:#06x}", read(channel, 0x1A));
+                info!("0x28 = {:#06x}", read(channel, 0x28));
+                info!("0x4E = {:#06x}", read(channel, 0x4E));
+                info!("0x4F = {:#06x}", read(channel, 0x4F));
+            } else {
+                // Based on "DRP State Machine" from XAPP888
+                // hold reset HIGH during pll config
+                reset(channel, true);
+                write(channel, 0x08, settings.clkout0_reg1);
+                write(channel, 0x09, settings.clkout0_reg2);
+                write(channel, 0x14, settings.clkfbout_reg1);
+                write(channel, 0x15, settings.clkfbout_reg2);
+                write(channel, 0x16, settings.div_reg);
+                write(channel, 0x18, settings.lock_reg1);
+                write(channel, 0x19, settings.lock_reg2);
+                write(channel, 0x1A, settings.lock_reg3);
+                write(channel, 0x28, settings.power_reg);
+                write(channel, 0x4E, settings.filt_reg1);
+                write(channel, 0x4F, settings.filt_reg2);
+                reset(channel, false);
+
+                // wait for the pll to lock
+                timer.delay_us(100);
+
+                let locked = unsafe { (CXP[channel].downconn_txpll_locked_read)() == 1 };
+                info!("txusrclk locked = {}", locked);
+            }
+        }
+
+        pub fn get_txusrclk_config(speed: CXP_SPEED) -> PLLSetting {
+            match speed {
+                CXP_SPEED::CXP_1 => {
+                    // CLKFBOUT_MULT = 8, DIVCLK_DIVIDE = 1 , CLKOUT0_DIVIDE = 32
+                    // TXUSRCLK=62.5MHz
+                    PLLSetting {
+                        clkout0_reg1: 0x1410,  //0x08
+                        clkout0_reg2: 0x0000,  //0x09
+                        clkfbout_reg1: 0x1104, //0x14
+                        clkfbout_reg2: 0x0000, //0x15
+                        div_reg: 0x1041,       //0x16
+                        lock_reg1: 0x03e8,     //0x18
+                        lock_reg2: 0x5801,     //0x19
+                        lock_reg3: 0xdbe9,     //0x1A
+                        power_reg: 0x0000,     //0x28
+                        filt_reg1: 0x9808,     //0x4E
+                        filt_reg2: 0x9100,     //0x4F
+                    }
+                }
+                CXP_SPEED::CXP_2 => {
+                    // CLKFBOUT_MULT = 8, DIVCLK_DIVIDE = 1 , CLKOUT0_DIVIDE = 16
+                    // TXUSRCLK=62.5MHz
+                    PLLSetting {
+                        clkout0_reg1: 0x1208,  //0x08
+                        clkout0_reg2: 0x0000,  //0x09
+                        clkfbout_reg1: 0x1104, //0x14
+                        clkfbout_reg2: 0x0000, //0x15
+                        div_reg: 0x1041,       //0x16
+                        lock_reg1: 0x03e8,     //0x18
+                        lock_reg2: 0x5801,     //0x19
+                        lock_reg3: 0xdbe9,     //0x1A
+                        power_reg: 0x0000,     //0x28
+                        filt_reg1: 0x9808,     //0x4E
+                        filt_reg2: 0x9100,     //0x4F
+                    }
+                }
+                CXP_SPEED::CXP_3 => {
+                    // CLKFBOUT_MULT = 10, DIVCLK_DIVIDE = 1 , CLKOUT0_DIVIDE = 16
+                    // TXUSRCLK=78.125MHz
+                    PLLSetting {
+                        clkout0_reg1: 0x1208,  //0x08
+                        clkout0_reg2: 0x0000,  //0x09
+                        clkfbout_reg1: 0x1145, //0x14
+                        clkfbout_reg2: 0x0000, //0x15
+                        div_reg: 0x1041,       //0x16
+                        lock_reg1: 0x03e8,     //0x18
+                        lock_reg2: 0x7001,     //0x19
+                        lock_reg3: 0xf3e9,     //0x1A
+                        power_reg: 0x0000,     //0x28
+                        filt_reg1: 0x9908,     //0x4E
+                        filt_reg2: 0x1900,     //0x4F
+                    }
+                }
+                CXP_SPEED::CXP_5 => {
+                    // CLKFBOUT_MULT = 8, DIVCLK_DIVIDE = 1 , CLKOUT0_DIVIDE = 8
+                    // TXUSRCLK=125MHz
+                    PLLSetting {
+                        clkout0_reg1: 0x1104,  //0x08
+                        clkout0_reg2: 0x0000,  //0x09
+                        clkfbout_reg1: 0x1104, //0x14
+                        clkfbout_reg2: 0x0000, //0x15
+                        div_reg: 0x1041,       //0x16
+                        lock_reg1: 0x03e8,     //0x18
+                        lock_reg2: 0x5801,     //0x19
+                        lock_reg3: 0xdbe9,     //0x1A
+                        power_reg: 0x0000,     //0x28
+                        filt_reg1: 0x9808,     //0x4E
+                        filt_reg2: 0x9100,     //0x4F
+                    }
+                }
+                CXP_SPEED::CXP_6 => {
+                    // CLKFBOUT_MULT = 10, DIVCLK_DIVIDE = 1 , CLKOUT0_DIVIDE = 8
+                    // TXUSRCLK=156.25MHz
+                    PLLSetting {
+                        clkout0_reg1: 0x1104,  //0x08
+                        clkout0_reg2: 0x0000,  //0x09
+                        clkfbout_reg1: 0x1145, //0x14
+                        clkfbout_reg2: 0x0000, //0x15
+                        div_reg: 0x1041,       //0x16
+                        lock_reg1: 0x03e8,     //0x18
+                        lock_reg2: 0x7001,     //0x19
+                        lock_reg3: 0xf3e9,     //0x1A
+                        power_reg: 0x0000,     //0x28
+                        filt_reg1: 0x9908,     //0x4E
+                        filt_reg2: 0x1900,     //0x4F
+                    }
+                }
+                CXP_SPEED::CXP_10 => {
+                    // CLKFBOUT_MULT = 8, DIVCLK_DIVIDE = 1 , CLKOUT0_DIVIDE = 4
+                    // TXUSRCLK=250MHz
+                    PLLSetting {
+                        clkout0_reg1: 0x1082,  //0x08
+                        clkout0_reg2: 0x0000,  //0x09
+                        clkfbout_reg1: 0x1104, //0x14
+                        clkfbout_reg2: 0x0000, //0x15
+                        div_reg: 0x1041,       //0x16
+                        lock_reg1: 0x03e8,     //0x18
+                        lock_reg2: 0x5801,     //0x19
+                        lock_reg3: 0xdbe9,     //0x1A
+                        power_reg: 0x0000,     //0x28
+                        filt_reg1: 0x9808,     //0x4E
+                        filt_reg2: 0x9100,     //0x4F
+                    }
+                }
+                CXP_SPEED::CXP_12 => {
+                    // CLKFBOUT_MULT = 10, DIVCLK_DIVIDE = 1 , CLKOUT0_DIVIDE = 4
+                    // TXUSRCLK=312.5MHz
+                    PLLSetting {
+                        clkout0_reg1: 0x1082,  //0x08
+                        clkout0_reg2: 0x0000,  //0x09
+                        clkfbout_reg1: 0x1145, //0x14
+                        clkfbout_reg2: 0x0000, //0x15
+                        div_reg: 0x1041,       //0x16
+                        lock_reg1: 0x03e8,     //0x18
+                        lock_reg2: 0x7001,     //0x19
+                        lock_reg3: 0xf3e9,     //0x1A
+                        power_reg: 0x0000,     //0x28
+                        filt_reg1: 0x9908,     //0x4E
+                        filt_reg2: 0x1900,     //0x4F
+                    }
+                }
+            }
+        }
+    }
+}

src/libboard_artiq/src/cxp_proto.rs

@@ -249,9 +249,9 @@ pub fn receive(channel: usize) -> Result<Option<DownConnPacket>, Error> {
         if (CXP[channel].downconn_pending_packet_read)() == 1 {
             let read_buffer_ptr = (CXP[channel].downconn_read_ptr_read)() as usize;
             println!("buffer ptr = {}", read_buffer_ptr);
-            let ptr = (CXP_RX_MEM[channel].base + read_buffer_ptr * BUF_LEN) as *mut u8;
+            let ptr = (CXP_RX_MEM[channel].base + read_buffer_ptr * BUF_LEN) as *mut u32;
 
-            let mut reader = Cursor::new(slice::from_raw_parts_mut(ptr, BUF_LEN));
+            let mut reader = Cursor::new(slice::from_raw_parts_mut(ptr as *mut u8, BUF_LEN));
             let packet_type = (CXP[channel].downconn_packet_type_read)();
 
             let packet = DownConnPacket::read_from(&mut reader, packet_type);
@@ -460,15 +460,14 @@ pub fn send(channel: usize, packet: &UpConnPacket) -> Result<(), Error> {
 
 fn send_data_packet(channel: usize, packet: &UpConnPacket) -> Result<(), Error> {
     unsafe {
-        // TODO: put this in mem group
-        while (CXP[channel].upconn_command_tx_read)() == 1 {}
+        while (CXP[channel].upconn_bootstrap_tx_busy_read)() == 1 {}
         let ptr = CXP_TX_MEM[0].base as *mut u32;
         let mut writer = Cursor::new(slice::from_raw_parts_mut(ptr as *mut u8, BUF_LEN));
 
         packet.write_to(&mut writer)?;
 
-        (CXP[channel].upconn_command_tx_word_len_write)(writer.position() as u16 / 4);
-        (CXP[channel].upconn_command_tx_write)(1);
+        (CXP[channel].upconn_bootstrap_tx_word_len_write)(writer.position() as u16 / 4);
+        (CXP[channel].upconn_bootstrap_tx_write)(1);
     }
 
     Ok(())
@@ -476,50 +475,44 @@ fn send_data_packet(channel: usize, packet: &UpConnPacket) -> Result<(), Error>
 
 fn send_test_packet(channel: usize) -> Result<(), Error> {
     unsafe {
-        while (CXP[channel].upconn_testseq_tx_read)() == 1 {}
-        (CXP[channel].upconn_tx_testmode_en_write)(1);
-        (CXP[channel].upconn_testseq_tx_write)(1);
-
-        // wait till all test packet is out before switching back
-        while (CXP[channel].upconn_testseq_tx_read)() == 1 {}
-        (CXP[channel].upconn_tx_testmode_en_write)(0);
+        while (CXP[channel].upconn_bootstrap_tx_busy_read)() == 1 {}
+        (CXP[channel].upconn_bootstrap_tx_testseq_write)(1);
     }
     Ok(())
 }
 
-//
-// DEBUG: use only
-//
-//
-//
-// pub fn write_u32(channel: usize, addr: u32, data: u32) -> Result<(), Error> {
-//     let mut data_slice: [u8; DATA_MAXSIZE] = [0; DATA_MAXSIZE];
-//     data_slice[..4].clone_from_slice(&data.to_be_bytes());
-//     send(
-//         channel,
-//         &UpConnPacket::CtrlWrite {
-//             tag: None,
-//             addr,
-//             length: 4,
-//             data: data_slice,
-//         },
-//     )?;
+pub fn write_u32(channel: u8, addr: u32, val: u32) -> Result<(), Error> {
+    // TODO: add tags after connection & verify it's CXPv2
 
-//     Ok(())
-// }
+    let mut data: [u8; DATA_MAXSIZE] = [0; DATA_MAXSIZE];
+    NetworkEndian::write_u32(&mut data[..4], val);
+    send(
+        channel as usize,
+        &UpConnPacket::CtrlWrite {
+            tag: None,
+            addr,
+            length: 4,
+            data,
+        },
+    )?;
 
-// pub fn read_u32(channel: usize, addr: u32) -> Result<(), Error> {
-//     send(
-//         channel,
-//         &UpConnPacket::CtrlRead {
-//             tag: None,
-//             addr,
-//             length: 4,
-//         },
-//     )?;
+    Ok(())
+}
 
-//     Ok(())
-// }
+pub fn read_u32(channel: u8, addr: u32) -> Result<(), Error> {
+    // TODO: add tags after connection & verify it's CXPv2
+
+    send(
+        channel as usize,
+        &UpConnPacket::CtrlRead {
+            tag: None,
+            addr,
+            length: 4,
+        },
+    )?;
+
+    Ok(())
+}
 
 // pub fn write_u64(channel: usize, addr: u32, data: u64) -> Result<(), Error> {
 //     let mut data_slice: [u8; DATA_MAXSIZE] = [0; DATA_MAXSIZE];
@@ -537,6 +530,11 @@ fn send_test_packet(channel: usize) -> Result<(), Error> {
 //     Ok(())
 // }
 
+//
+// DEBUG: use only
+//
+//
+//
 pub fn print_packet(pak: &[u8]) {
     println!("pak = [");
     for i in 0..(pak.len() / 4) {
@@ -573,14 +571,14 @@ pub fn print_packetu32(pak: &[u32], k: &[u8]) {
 
 pub fn downconn_debug_send(channel: usize, packet: &UpConnPacket) -> Result<(), Error> {
     unsafe {
-        while (CXP[channel].downconn_command_tx_read)() == 1 {}
+        while (CXP[channel].downconn_bootstrap_loopback_tx_busy_read)() == 1 {}
         let ptr = CXP_LOOPBACK_MEM[0].base as *mut u32;
         let mut writer = Cursor::new(slice::from_raw_parts_mut(ptr as *mut u8, BUF_LEN));
 
         packet.write_to(&mut writer)?;
 
-        (CXP[channel].downconn_command_tx_word_len_write)(writer.position() as u16 / 4);
-        (CXP[channel].downconn_command_tx_write)(1);
+        (CXP[channel].downconn_bootstrap_loopback_tx_word_len_write)(writer.position() as u16 / 4);
+        (CXP[channel].downconn_bootstrap_loopback_tx_write)(1);
     }
 
     Ok(())
@@ -588,8 +586,8 @@ pub fn downconn_debug_send(channel: usize, packet: &UpConnPacket) -> Result<(),
 
 pub fn downconn_debug_mem_print(channel: usize) {
     unsafe {
-        let ptr = CXP_RX_MEM[channel].base as *mut u8;
-        let arr = slice::from_raw_parts_mut(ptr, BUF_LEN * 4);
+        let ptr = CXP_RX_MEM[channel].base as *mut u32;
+        let arr = slice::from_raw_parts_mut(ptr as *mut u8, BUF_LEN * 4);
         print_packet(arr);
     }
 }
@@ -602,12 +600,7 @@ pub fn downconn_debug_send_trig_ack(channel: usize) {
 
 pub fn downconn_send_test_packet(channel: usize) {
     unsafe {
-        while (CXP[channel].downconn_testseq_tx_read)() == 1 {}
-        (CXP[channel].downconn_mux_sel_write)(1);
-        (CXP[channel].downconn_testseq_tx_write)(1);
-
-        // wait till all test packet is out before switching back
-        while (CXP[channel].downconn_testseq_tx_read)() == 1 {}
-        (CXP[channel].downconn_mux_sel_write)(0);
+        while (CXP[channel].downconn_bootstrap_loopback_tx_busy_read)() == 1 {}
+        (CXP[channel].downconn_bootstrap_loopback_tx_testseq_write)(1);
     }
 }

src/libboard_artiq/src/cxp_upconn.rs

@@ -9,18 +9,12 @@ pub fn tx_test(channel: usize, timer: &mut GlobalTimer) {
     let mut pak_arr: [u8; LEN] = [0; LEN];
 
     unsafe {
-        (CXP[channel].upconn_clk_reset_write)(1);
-        // CXP[channel].upconn_bitrate2x_enable_write(1);
-        (CXP[channel].upconn_clk_reset_write)(0);
-
-        (CXP[channel].upconn_tx_enable_write)(1);
-        timer.delay_us(2); // send one word
         // cxp_proto::read_u32(channel, 0x00).expect("Cannot Write CoaXpress Register");
         // cxp_proto::write_u64(channel, 0x00, 0x01);
         // cxp_proto::send(channel, &cxp_proto::Packet::EventAck { packet_tag: 0x04 }).expect("Cannot send CoaXpress packet");
         // cxp_proto::send(channel, &cxp_proto::Packet::TestPacket).expect("Cannot send CoaXpress packet");
 
-        timer.delay_us(2);
+        timer.delay_us(2); // send one word
         // DEBUG: Trigger packet
         (CXP[channel].upconn_trig_delay_write)(0x86);
         (CXP[channel].upconn_linktrigger_write)(0x00);

src/libboard_artiq/src/lib.rs

@@ -50,6 +50,8 @@ pub mod cxp_upconn;
 
 pub mod cxp_proto;
 
+pub mod cxp_phys;
+
 pub fn identifier_read(buf: &mut [u8]) -> &str {
     unsafe {
         pl::csr::identifier::address_write(0);

src/libksupport/src/cxp.rs

@@ -0,0 +1,11 @@
+use libboard_artiq::cxp_proto;
+
+pub extern "C" fn cxp_readu32(channel: i32, addr: i32) {
+    // TODO: use artiq_raise like i2c?
+    cxp_proto::read_u32(channel as u8, addr as u32).expect("CXP transmission failed");
+}
+
+pub extern "C" fn cxp_writeu32(channel: i32, addr: i32, val: i32) {
+    // TODO: use artiq_raise like i2c?
+    cxp_proto::write_u32(channel as u8, addr as u32, val as u32).expect("CXP transmission failed");
+}

src/libksupport/src/kernel/api.rs

@@ -11,6 +11,8 @@ use super::{cache,
             core1::rtio_get_destination_status,
             dma, linalg,
             rpc::{rpc_recv, rpc_send, rpc_send_async}};
+#[cfg(has_cxp_phys)]
+use crate::cxp;
 use crate::{eh_artiq, i2c, rtio};
 
 extern "C" {
@@ -126,6 +128,12 @@ pub fn resolve(required: &[u8]) -> Option<u32> {
         #[cfg(has_drtio)]
         api!(subkernel_await_message = subkernel::await_message),
 
+        // CoaXPress
+        #[cfg(has_cxp_phys)]
+        api!(cxp_readu32 = cxp::cxp_readu32),
+        #[cfg(has_cxp_phys)]
+        api!(cxp_writeu32 = cxp::cxp_writeu32),
+
         // Double-precision floating-point arithmetic helper functions
         // RTABI chapter 4.1.2, Table 2
         api!(__aeabi_dadd),

src/libksupport/src/lib.rs

@@ -35,6 +35,8 @@ pub mod rtio;
 #[path = "../../../build/pl.rs"]
 pub mod pl;
 
+#[cfg(has_cxp_phys)]
+pub mod cxp;
 
 #[derive(Debug, Clone)]
 pub struct RPCException {

src/runtime/src/main.rs

@@ -17,7 +17,7 @@ use libasync::task;
 use libboard_artiq::drtio_eem;
 #[cfg(feature = "target_kasli_soc")]
 use libboard_artiq::io_expander;
-use libboard_artiq::{cxp_downconn, cxp_proto, cxp_upconn, identifier_read, logger, pl};
+use libboard_artiq::{cxp_downconn, cxp_phys, cxp_proto, cxp_upconn, identifier_read, logger, pl};
 use libboard_zynq::{gic, mpcore, timer::GlobalTimer};
 use libconfig::Config;
 use libcortex_a9::l2c::enable_l2_cache;
@@ -150,19 +150,19 @@ pub fn main_core0() {
 
     task::spawn(ksupport::report_async_rtio_errors());
 
-    cxp_downconn::setup(&mut timer);
-    // cxp_downconn::loopback_testing(0, &mut timer, cxp_downconn::CXP_SPEED::CXP_1);
-    // cxp_downconn::loopback_testing(0, &mut timer, cxp_downconn::CXP_SPEED::CXP_2);
-    // cxp_downconn::loopback_testing(0, &mut timer, cxp_downconn::CXP_SPEED::CXP_3);
-    // cxp_downconn::loopback_testing(0, &mut timer, cxp_downconn::CXP_SPEED::CXP_5);
-    // cxp_downconn::loopback_testing(0, &mut timer, cxp_downconn::CXP_SPEED::CXP_6);
-    // cxp_downconn::loopback_testing(0, &mut timer, cxp_downconn::CXP_SPEED::CXP_10);
-    // cxp_downconn::loopback_testing(0, &mut timer, cxp_downconn::CXP_SPEED::CXP_12);
-    loop {
-        use embedded_hal::prelude::_embedded_hal_blocking_delay_DelayUs;
-        cxp_upconn::tx_test(0, &mut timer);
-        timer.delay_us(5_000_000);
-    }
+    cxp_phys::setup(&mut timer);
+    cxp_downconn::loopback_testing(0, &mut timer, cxp_phys::CXP_SPEED::CXP_1);
+    // cxp_downconn::loopback_testing(0, &mut timer, cxp_phys::CXP_SPEED::CXP_2);
+    // cxp_downconn::loopback_testing(0, &mut timer, cxp_phys::CXP_SPEED::CXP_3);
+    // cxp_downconn::loopback_testing(0, &mut timer, cxp_phys::CXP_SPEED::CXP_5);
+    // cxp_downconn::loopback_testing(0, &mut timer, cxp_phys::CXP_SPEED::CXP_6);
+    // cxp_downconn::loopback_testing(0, &mut timer, cxp_phys::CXP_SPEED::CXP_10);
+    // cxp_downconn::loopback_testing(0, &mut timer, cxp_phys::CXP_SPEED::CXP_12);
+    // loop {
+    //     use embedded_hal::prelude::_embedded_hal_blocking_delay_DelayUs;
+    //     cxp_upconn::tx_test(0, &mut timer);
+    //     timer.delay_us(5_000_000);
+    // }
 
     comms::main(timer, cfg);
 }