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pipeline GW: merge testseq into tx packet

This commit is contained in:
morgan 2024-10-10 13:06:36 +08:00
parent da722fce2b
commit aa4594d84a
1 changed files with 22 additions and 48 deletions
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70
src/gateware/cxp_pipeline.py
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@ -180,10 +180,13 @@ class Trigger_ACK_Inserter(Module):
@FullMemoryWE()
class TX_Command_Packet(Module, AutoCSR):
class TX_Bootstrap(Module, AutoCSR):
def __init__(self):
self.tx_word_len = CSRStorage(log2_int(buffer_depth))
self.tx = CSR()
self.tx_testseq = CSR()
self.tx_busy = CSRStatus()
# # #
@ -191,20 +194,13 @@ class TX_Command_Packet(Module, AutoCSR):
self.specials.mem_port = mem_port = mem.get_port()
self.source = stream.Endpoint(word_layout)
tx_done = Signal()
# increment addr in the same cycle the moment addr_inc is high
# as memory takes one cycle to shift to the correct addr
addr_next = Signal(log2_int(buffer_depth))
addr = Signal.like(addr_next)
addr_rst = Signal()
addr_inc = Signal()
# increment addr in the same cycle the moment addr_inc is high
# as memory takes one cycle to shift to the correct addr
self.sync += [
addr.eq(addr_next),
If(self.tx.re, self.tx.w.eq(1)),
If(tx_done, self.tx.w.eq(0)),
]
self.sync += addr.eq(addr_next),
self.comb += [
addr_next.eq(addr),
@ -218,11 +214,18 @@ class TX_Command_Packet(Module, AutoCSR):
]
self.submodules.fsm = fsm = FSM(reset_state="IDLE")
self.sync += self.tx_busy.status.eq(~fsm.ongoing("IDLE"))
cnt = Signal(max=0xFFF)
fsm.act("IDLE",
addr_rst.eq(1),
If(self.tx.re, NextState("TRANSMIT"))
If(self.tx.re, NextState("TRANSMIT")),
If(self.tx_testseq.re,
NextValue(cnt, cnt.reset),
NextState("WRITE_TEST_PACKET_TYPE"),
)
)
fsm.act("TRANSMIT",
self.source.stb.eq(1),
If(self.source.ack,
@ -230,35 +233,11 @@ class TX_Command_Packet(Module, AutoCSR):
),
If(addr_next == self.tx_word_len.storage,
self.source.eop.eq(1),
tx_done.eq(1),
NextState("IDLE")
)
)
class TX_Test_Packet(Module, AutoCSR):
def __init__(self):
self.tx = CSR()
# # #
tx_done = Signal()
self.sync += [
If(self.tx.re, self.tx.w.eq(1)),
If(tx_done, self.tx.w.eq(0)),
]
self.source = stream.Endpoint(word_layout)
self.submodules.fsm = fsm = FSM(reset_state="IDLE")
cnt = Signal(max=0xFFF)
fsm.act("IDLE",
NextValue(cnt, cnt.reset),
If(self.tx.re,
NextState("WRITE_PACKET_TYPE")
)
)
fsm.act("WRITE_PACKET_TYPE",
fsm.act("WRITE_TEST_PACKET_TYPE",
self.source.stb.eq(1),
self.source.data.eq(Replicate(C(0x04, char_width), 4)),
self.source.k.eq(0b0000),
@ -271,7 +250,6 @@ class TX_Test_Packet(Module, AutoCSR):
self.source.k.eq(0b0000),
If(self.source.ack,
If(cnt == 0xFFF-3,
tx_done.eq(1),
self.source.eop.eq(1),
NextState("IDLE")
).Else(
@ -281,8 +259,6 @@ class TX_Test_Packet(Module, AutoCSR):
)
)
class RX_Debug_Buffer(Module,AutoCSR):
def __init__(self):
self.submodules.buf_out = buf_out = stream.SyncFIFO(word_layout, 128)
@ -302,26 +278,24 @@ class RX_Debug_Buffer(Module,AutoCSR):
]
class Duplicate_Majority_Voter(Module):
def __init__(self, data, k):
assert data.nbits == 32
assert k.nbits == 4
def __init__(self, char_4x, k_4x):
assert char_4x.nbits == 32
assert k_4x.nbits == 4
# Section 9.2.2.1 (CXP-001-2021)
# decoder should immune to single bit errors when handling duplicated characters
self.char = Signal(char_width)
self.k = Signal()
a, a_k = data[:8], k[0]
b, b_k = data[8:16], k[1]
c, c_k = data[16:24], k[2]
d, d_k = data[24:], k[3]
a, b, c, d = [char_4x[i*8:(i+1)*8] for i in range(4)]
a_k, b_k, c_k, d_k = [k_4x[i:(i+1)] for i in range(4)]
self.comb += [
self.char.eq(a&b&c | a&b&d | a&c&d | b&c&d),
self.k.eq(a_k&b_k&c_k | a_k&b_k&d_k | a_k&c_k&d_k | b_k&c_k&d_k),
]
@FullMemoryWE()
class CXP_Data_Packet_Decode(Module):
class RX_Bootstrap(Module):
def __init__(self):
self.packet_type = Signal(8)