Comparing 59e3b2f1c4..9016a5eebf - artiq-zynq - M-Labs Git

morgan

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artiq-zynq

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Author	SHA1	Message	Date
morgan	9016a5eebf	cxp protocol: init testing: add packet printing helper function testing: add rx loopback proto FW: use memory buffer for tx and rx proto FW: use byteoder crate to handle endianness proto FW: add event packet reader and writer proto FW: add error correction for 4x char	2024-10-10 13:02:06 +08:00
morgan	77d38aad63	Cargo: add byteorder	2024-10-10 13:02:06 +08:00
morgan	b8a39e7904	lib: compile mem with cxp	2024-10-10 13:02:06 +08:00
morgan	b0b0a00bc9	main: add testing runtime main: move lib location main: add testing channel	2024-10-10 12:59:36 +08:00
morgan	8161700550	cxp downconn firmware: GTX setup testing: add loopmode mode & tsusrclk mmcm drp bitbang testing: add IDLE word printout testing: add tx packet to test packet decoder downconn: add QPLL and GTX setup downconn: add DRP to support all CXP linerate up to 12.5Gbps	2024-10-10 12:59:36 +08:00
morgan	6daf653f73	cxp upconn firmware: low speed serial setup testing: add trigger & trigger ack CSR to test tranmission prioirty upconn: add some upconn error for control flow upconn: add control packet writer control packet: add u32 & u64 register control control packet: add CRC calculation & packet type inserter in fw	2024-10-10 12:59:36 +08:00
morgan	4d03154e63	zc706: add CXP_DEMO variant zc706: add fmc pads zc706: add constraint to fix comma alignment & setup/hold time issue zc706: add csr & mem group for cxp	2024-10-10 12:59:36 +08:00
morgan	9f80acd9ba	cxp: add PHY and pipeline testing: add loopback tx for rx testing testing: add trigger, trigger ack for testing cxp: add upconn & downconn phy cxp: add upconn & downconn pipeline	2024-10-10 12:59:36 +08:00
morgan	12d8aed1d8	cxp pipeline: packet handling pipeline tx pipeline: add CRC32 inserter tx pipeline: add start & end of packet code inserter tx pipeline: add packet wrapper for start & stop packet indication tx pipeline: add code source for trigger & trigger ack packet tx pipeline: add packet for trigger & trigger ack tx pipeline: add test packet generator tx pipeline: add tx_command_packet for firmware tx command packet: add dma to store control packet rx pipeline: add reciever path rx pipeline: add trig ack checker rx pipeline: add packet decoder decoder: add test packet checher decoder: add packet DMA	2024-10-10 12:59:36 +08:00
morgan	989df99c31	cxp upconn gw: add low speed serial PHY testing: add debug fifo output b4 encoder cxp upconn: add low speed serial cxp upconn: add reset, tx_busy, tx_enable cxp upconn: add clockgen module for 20.83Mbps & 41.66Mbps using counters cxp upconn: add oserdes using CEInserter	2024-10-10 12:59:36 +08:00
morgan	75d41c3787	cxp downconn gw: add gtx up to 12.5Gbps testing: add txusrclk mmcm & loopback mode testing: add debug output testing: send comma in the middle of long packet to maintain lock downconn: don't put IDLE into fifo downconn: add GTX and QPLL support downconn: add DRP for GTX and QPLL to support all CXP linerates GTX: add gtx with mmcm for TXUSRCLK freq requirement GTX: add loopback mode parameter for testing GTX: add gtx with 40bits internal width GTX: use built-in comma aligner GTX: add comma checker to ensure comma is aligner on highest linerate GTX: set QPLL as CLK source for GTX	2024-10-10 12:58:41 +08:00

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