forked from M-Labs/artiq-zynq
cxp upconn firmware: low speed serial setup
testing: add trigger & trigger ack CSR to test tranmission prioirty upconn: add some upconn error for control flow upconn: add control packet writer control packet: add u32 & u64 register control control packet: add CRC calculation & packet type inserter in fw
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@ -0,0 +1,48 @@
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use embedded_hal::prelude::_embedded_hal_blocking_delay_DelayUs;
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use libboard_zynq::timer::GlobalTimer;
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pub use crate::cxp_proto;
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use crate::pl::{csr, csr::CXP};
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pub fn tx_test(channel: usize, timer: &mut GlobalTimer) {
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const LEN: usize = 4 * 30;
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let mut pak_arr: [u8; LEN] = [0; LEN];
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unsafe {
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(CXP[channel].upconn_clk_reset_write)(1);
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// CXP[channel].upconn_bitrate2x_enable_write(1);
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(CXP[channel].upconn_clk_reset_write)(0);
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(CXP[channel].upconn_tx_enable_write)(1);
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timer.delay_us(2); // send one word
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// cxp_proto::read_u32(channel, 0x00).expect("Cannot Write CoaXpress Register");
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// cxp_proto::write_u64(channel, 0x00, 0x01);
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// cxp_proto::send(channel, &cxp_proto::Packet::EventAck { packet_tag: 0x04 }).expect("Cannot send CoaXpress packet");
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// cxp_proto::send(channel, &cxp_proto::Packet::TestPacket).expect("Cannot send CoaXpress packet");
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timer.delay_us(2);
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// DEBUG: Trigger packet
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(CXP[channel].upconn_trig_delay_write)(0x86);
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(CXP[channel].upconn_linktrigger_write)(0x00);
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(CXP[channel].upconn_trig_stb_write)(1); // send trig
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// DEBUG: Trigger ACK packet
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// CXP[channel].upconn_ack_write(1);
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timer.delay_us(20);
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(CXP[channel].upconn_tx_enable_write)(0);
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// Collect data
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let mut i: usize = 0;
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while csr::cxp_phys::upconn_tx0_debug_buf_dout_valid_read() == 1 {
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pak_arr[i] = csr::cxp_phys::upconn_tx0_debug_buf_dout_pak_read();
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csr::cxp_phys::upconn_tx0_debug_buf_inc_write(1);
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i += 1;
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if i == LEN {
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break;
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}
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}
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cxp_proto::print_packet(&pak_arr);
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}
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}
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@ -42,6 +42,9 @@ pub mod si5324;
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pub mod si549;
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use core::{cmp, str};
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#[cfg(has_cxp_phys)]
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pub mod cxp_upconn;
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pub fn identifier_read(buf: &mut [u8]) -> &str {
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unsafe {
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pl::csr::identifier::address_write(0);
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