forked from M-Labs/artiq-zynq
cxp GW: add buffer error csr & read ptr cdc
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parent
11f47debd1
commit
feb621d003
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@ -209,16 +209,18 @@ class DownConn_Interface(Module, AutoCSR):
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# Priority level 2 packet - data, test packet
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self.submodules.packet_decoder = packet_decoder = cdr(CXP_Data_Packet_Decode())
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self.new_rx_packet = CSR()
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self.decoder_error = CSR()
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self.test_error = CSR()
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self.buffer_error = CSR()
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decode_err_ps = PulseSynchronizer("cxp_gtx_rx", "sys")
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test_err_ps = PulseSynchronizer("cxp_gtx_rx", "sys")
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self.submodules += decode_err_ps, test_err_ps
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buffer_err_ps = PulseSynchronizer("cxp_gtx_rx", "sys")
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self.submodules += decode_err_ps, test_err_ps, buffer_err_ps
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self.comb += [
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decode_err_ps.i.eq(packet_decoder.decode_err),
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test_err_ps.i.eq(packet_decoder.test_err),
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buffer_err_ps.i.eq(packet_decoder.buffer_err),
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]
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self.sync += [
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If(decode_err_ps.o,
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@ -231,6 +233,11 @@ class DownConn_Interface(Module, AutoCSR):
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).Elif(self.test_error.re,
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self.test_error.w.eq(0),
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),
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If(buffer_err_ps.o,
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self.buffer_error.w.eq(1),
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).Elif(self.test_error.re,
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self.buffer_error.w.eq(0),
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),
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]
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@ -239,7 +246,10 @@ class DownConn_Interface(Module, AutoCSR):
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self.pending_packet = CSR()
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self.read_ptr = CSRStatus(log2_int(buffer_count))
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self.specials += MultiReg(packet_decoder.packet_type, self.packet_type.status),
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self.specials += [
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MultiReg(packet_decoder.packet_type, self.packet_type.status),
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MultiReg(self.read_ptr.status, packet_decoder.read_ptr_rx, odomain="cxp_gtx_rx"),
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]
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self.sync += [
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self.pending_packet.w.eq(self.read_ptr.status != packet_decoder.write_ptr_sys),
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If(self.pending_packet.re & self.pending_packet.w,
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