forked from M-Labs/artiq-zynq
pipeline GW: add buffer error
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d3e0cc2819
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@ -305,8 +305,10 @@ class RX_Debug_Buffer(Module,AutoCSR):
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class CXP_Data_Packet_Decode(Module):
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def __init__(self):
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self.packet_type = Signal(8)
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self.decode_err = Signal()
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self.test_err = Signal()
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self.buffer_err = Signal()
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# # #
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# DEBUG: remove debug
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@ -417,6 +419,8 @@ class CXP_Data_Packet_Decode(Module):
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self.write_ptr_sys = Signal.like(write_ptr)
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self.specials += MultiReg(write_ptr, self.write_ptr_sys),
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self.read_ptr_rx = Signal.like(write_ptr)
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self.comb += [
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mem_port.adr[:addr_nbits].eq(addr),
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mem_port.adr[addr_nbits:].eq(write_ptr),
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@ -429,16 +433,32 @@ class CXP_Data_Packet_Decode(Module):
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self.sink.ack.eq(1),
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If(self.sink.stb,
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If(((self.sink.data == Replicate(KCode["pak_end"], 4)) & (self.sink.k == 0b1111)),
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NextValue(write_ptr, write_ptr + 1),
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NextState("IDLE"),
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NextState("MOVE_BUFFER_PTR"),
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).Else(
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mem_port.we.eq(1),
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mem_port.dat_w.eq(self.sink.data),
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NextValue(addr, addr + 1),
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If(addr == buffer_depth - 1,
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# discard the packet
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self.buffer_err.eq(1),
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NextState("IDLE"),
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)
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)
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)
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)
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fsm.act("MOVE_BUFFER_PTR",
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self.sink.ack.eq(0),
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If(write_ptr + 1 == self.read_ptr_rx,
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# if next one hasn't been read, overwrite the current buffer when new packet comes in
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self.buffer_err.eq(1),
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).Else(
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NextValue(write_ptr, write_ptr + 1),
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),
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NextState("IDLE"),
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)
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class CXP_Trig_Ack_Checker(Module, AutoCSR):
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def __init__(self):
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self.sink = stream.Endpoint(word_layout)
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