forked from M-Labs/artiq-zynq
zc706: add constraint to fix comma alignment issue
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@ -695,6 +695,11 @@ class CXP_FMC():
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)
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self.csr_devices.append("cxp")
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# max freq of cxp_gtx_rx = linerate/internal_datawidth = 12.5Gbps/40 = 312.5MHz
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platform.add_period_constraint(self.cxp.downconn.gtx.cd_cxp_gtx_tx.clk, 3.2)
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platform.add_period_constraint(self.cxp.downconn.gtx.cd_cxp_gtx_rx.clk, 3.2)
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platform.add_false_path_constraints(self.cxp.downconn.gtx.cd_cxp_gtx_tx.clk, self.cxp.downconn.gtx.cd_cxp_gtx_rx.clk)
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rtio_channels = []
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# FIXME remove this placeholder RTIO channel
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# There are too few RTIO channels and cannot be compiled (adr width issue of the lane distributor)
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