forked from M-Labs/artiq-zynq
zc706: update naming
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@ -26,7 +26,7 @@ import acpki
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import drtio_aux_controller
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import zynq_clocking
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import cxp_4r_fmc
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import cxp, cxp_frame_pipeline
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import cxp
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from config import write_csr_file, write_mem_file, write_rustc_cfg_file
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class SMAClkinForward(Module):
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@ -707,7 +707,7 @@ class CXP_FMC():
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rtio_channels = []
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cxp_csr_group = []
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cxp_mem_group = []
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cxp_downconns = []
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cxp_rx_pipelines = []
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for i, phy in enumerate(cxp_phys.phys):
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cxp_name = "cxp" + str(i)
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@ -724,7 +724,7 @@ class CXP_FMC():
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self.csr_devices.append(cxp_name)
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cxp_csr_group.append(cxp_name)
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cxp_downconns.append(cxp_interface.get_rx_downconn())
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cxp_rx_pipelines.append(cxp_interface.get_rx_pipeline())
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# Add memory group
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@ -739,7 +739,7 @@ class CXP_FMC():
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self.add_memory_group("cxp_mem", cxp_mem_group)
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self.add_csr_group("cxp", cxp_csr_group)
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self.submodules.cxp_frame_pipeline = cxp.CXP_Frame_Pipeline(cxp_downconns, pmod_pads)
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self.submodules.cxp_frame_pipeline = cxp.CXP_Frame_Pipeline(cxp_rx_pipelines, pmod_pads)
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self.csr_devices.append("cxp_frame_pipeline")
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