cxp pipeline: add trigger ack

src/gateware/cxp_pipeline.py

@@ -6,6 +6,64 @@ from misoc.cores.liteeth_mini.mac.crc import LiteEthMACCRCEngine, LiteEthMACCRCI
 def K(x, y):
     return ((y << 5) | x)
 
+class Trigger_ACK(Module):
+    def __init__(self, layout):
+        self.ack = Signal()
+
+        self.source = source = stream.Endpoint(layout)
+
+        # # #
+
+        # Section 9.3.2 (CXP-001-2021)
+        # Send 4x K28.6 and 4x 0x01 as trigger packet ack
+
+        cnt = Signal(max=4)
+        clr_cnt = Signal()
+        inc_cnt = Signal()
+
+        self.sync += [
+            If(clr_cnt,
+                cnt.eq(cnt.reset),
+            ).Elif(inc_cnt,
+                cnt.eq(cnt + 1),
+            )
+        ]
+
+        self.submodules.fsm = fsm = FSM(reset_state="IDLE")
+
+        fsm.act("IDLE",
+            clr_cnt.eq(1),
+            If(self.ack,
+               NextState("WRITE_ACK0")
+            )
+        )
+
+        fsm.act("WRITE_ACK0",
+            source.stb.eq(1),
+            source.data.eq(K(28, 6)),
+            source.k.eq(1),
+            If(cnt == 3,
+                clr_cnt.eq(1),
+                If(source.ack, NextState("WRITE_ACK1"))
+            ).Else(
+                inc_cnt.eq(source.ack)
+            )
+        )
+
+        fsm.act("WRITE_ACK1",
+            source.stb.eq(1),
+            source.data.eq(0x01),
+            source.k.eq(0),
+            If(cnt == 3,
+                source.eop.eq(1),
+                If(source.ack, NextState("IDLE"))
+            ).Else(
+                inc_cnt.eq(source.ack)
+            )
+        )
+
+        
+
 class Code_Inserter(Module):
     def __init__(self, layout, insert_infront=True, counts=4):
         self.sink = sink = stream.Endpoint(layout)
@@ -54,15 +112,12 @@ class Code_Inserter(Module):
 
             fsm.act("COPY",
                 sink.connect(source),
-
                 If(sink.stb & sink.eop & source.ack,
                     NextState("IDLE"),
                 )
-            
             )
 
         else:
-
             fsm.act("IDLE",
                 sink.ack.eq(1),
                 clr_cnt.eq(1),