forked from M-Labs/artiq-zynq
cxp pipeline: fix code inserter at the end
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91a73c225d
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@ -22,7 +22,7 @@ class Code_Inserter(Module):
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self.sync += [
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If(clr_cnt,
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cnt.eq(0),
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cnt.eq(cnt.reset),
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).Elif(inc_cnt,
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cnt.eq(cnt + 1),
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)
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@ -55,7 +55,6 @@ class Code_Inserter(Module):
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fsm.act("COPY",
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sink.connect(source),
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# eop = end of packet?
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If(sink.stb & sink.eop & source.ack,
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NextState("IDLE"),
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)
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@ -66,6 +65,7 @@ class Code_Inserter(Module):
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fsm.act("IDLE",
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sink.ack.eq(1),
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clr_cnt.eq(1),
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If(sink.stb,
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sink.ack.eq(0),
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NextState("COPY"),
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