forked from M-Labs/artiq-zynq
cxp GW: rname to rxphys
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034588ec59
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@ -1,10 +1,10 @@
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from migen import *
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from migen.genlib.cdc import MultiReg, PulseSynchronizer, BusSynchronizer
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from migen.genlib.cdc import MultiReg, PulseSynchronizer
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from misoc.interconnect.csr import *
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from artiq.gateware.rtio import rtlink
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from cxp_downconn import CXP_DownConn_PHYS
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from cxp_downconn import CXP_RXPHYs
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from cxp_upconn import CXP_TXPHYs
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from cxp_pipeline import *
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from cxp_frame_pipeline import *
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@ -18,10 +18,10 @@ class CXP_PHYS(Module, AutoCSR):
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assert len(upconn_pads) == len(downconn_pads)
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self.submodules.tx = CXP_TXPHYs(upconn_pads, sys_clk_freq, debug_sma, pmod_pads)
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self.submodules.downconn = CXP_DownConn_PHYS(refclk, downconn_pads, sys_clk_freq, debug_sma, pmod_pads)
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self.submodules.rx = CXP_RXPHYs(refclk, downconn_pads, sys_clk_freq, debug_sma, pmod_pads)
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self.phys = []
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for tx, rx in zip(self.tx.phys, self.downconn.rx_phys):
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for tx, rx in zip(self.tx.phys, self.rx.phys):
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phy = SimpleNamespace()
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phy.tx, phy.rx = tx, rx
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self.phys.append(phy)
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