From ec84a332c73ea5f4deff4ccea3128c5c9aacf495 Mon Sep 17 00:00:00 2001 From: morgan Date: Tue, 14 Jan 2025 13:04:12 +0800 Subject: [PATCH] cxp GW: rname to rxphys --- src/gateware/cxp.py | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/gateware/cxp.py b/src/gateware/cxp.py index 7799be8..28c1785 100644 --- a/src/gateware/cxp.py +++ b/src/gateware/cxp.py @@ -1,10 +1,10 @@ from migen import * -from migen.genlib.cdc import MultiReg, PulseSynchronizer, BusSynchronizer +from migen.genlib.cdc import MultiReg, PulseSynchronizer from misoc.interconnect.csr import * from artiq.gateware.rtio import rtlink -from cxp_downconn import CXP_DownConn_PHYS +from cxp_downconn import CXP_RXPHYs from cxp_upconn import CXP_TXPHYs from cxp_pipeline import * from cxp_frame_pipeline import * @@ -18,10 +18,10 @@ class CXP_PHYS(Module, AutoCSR): assert len(upconn_pads) == len(downconn_pads) self.submodules.tx = CXP_TXPHYs(upconn_pads, sys_clk_freq, debug_sma, pmod_pads) - self.submodules.downconn = CXP_DownConn_PHYS(refclk, downconn_pads, sys_clk_freq, debug_sma, pmod_pads) + self.submodules.rx = CXP_RXPHYs(refclk, downconn_pads, sys_clk_freq, debug_sma, pmod_pads) self.phys = [] - for tx, rx in zip(self.tx.phys, self.downconn.rx_phys): + for tx, rx in zip(self.tx.phys, self.rx.phys): phy = SimpleNamespace() phy.tx, phy.rx = tx, rx self.phys.append(phy)