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cxp upconn : fix idle word lag behind tx_wordcount

This commit is contained in:
morgan 2024-06-28 15:46:13 +08:00
parent 8ba7793b24
commit dbf7ac1cb9
1 changed files with 24 additions and 7 deletions
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31
src/gateware/cxp_upconn.py
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@ -99,20 +99,33 @@ class CXP_UpConn(Module, AutoCSR):
) )
) )
idle_ack = Signal()
# CXP 2.1 section 9.2.4 # CXP 2.1 section 9.2.4
# Higher priority packet can be inserted into a lower priority packet during transmission # Higher priority packet can be inserted into a lower priority packet during transmission
# Priority lv 0 can be inserted in char boundary of the packet # Priority lv 0 can be inserted in char boundary of the packet
# Priority lv 1-2 need to be inserted in word boundary of the packet # Priority lv 1-2 need to be inserted in word boundary of the packet
self.sync.cxp_upconn += [ self.sync.cxp_upconn += [
self.tx_fifos.disp_in.eq(disp),
self.encoder.disp_in.eq(disp),
self.encoder.d.eq(Array(IDLE_CHARS)[tx_wordcount][0]),
self.encoder.k.eq(Array(IDLE_CHARS)[tx_wordcount][1]),
If(tx_en, If(tx_en,
o.eq(tx_reg[0]), o.eq(tx_reg[0]),
tx_reg.eq(Cat(tx_reg[1:], 0)), tx_reg.eq(Cat(tx_reg[1:], 0)),
tx_bitcount.eq(tx_bitcount + 1), tx_bitcount.eq(tx_bitcount + 1),
self.tx_fifos.disp_in.eq(disp),
self.encoder.disp_in.eq(disp),
If(idle_ack,
# reset after asserted
idle_ack.eq(0),
If(tx_wordcount == 3,
self.encoder.d.eq(Array(IDLE_CHARS)[0][0]),
self.encoder.k.eq(Array(IDLE_CHARS)[0][1]),
).Else(
self.encoder.d.eq(Array(IDLE_CHARS)[tx_wordcount + 1][0]),
self.encoder.k.eq(Array(IDLE_CHARS)[tx_wordcount + 1][1]),
)
),
# char boundary # char boundary
If(tx_bitcount == 9, If(tx_bitcount == 9,
tx_bitcount.eq(0), tx_bitcount.eq(0),
@ -129,16 +142,19 @@ class CXP_UpConn(Module, AutoCSR):
tx_wordcount.eq(0), tx_wordcount.eq(0),
), ),
# word boundary # new word boundary
If(tx_wordcount == 0, If(tx_wordcount == 3,
If(~self.tx_fifos.pe.n, If(~self.tx_fifos.pe.n,
idling.eq(0), idling.eq(0),
priority.eq(self.tx_fifos.pe.o), priority.eq(self.tx_fifos.pe.o),
self.tx_fifos.source_ack[self.tx_fifos.pe.o].eq(1), self.tx_fifos.source_ack[self.tx_fifos.pe.o].eq(1),
tx_reg.eq(self.tx_fifos.source_data[self.tx_fifos.pe.o]), tx_reg.eq(self.tx_fifos.source_data[self.tx_fifos.pe.o]),
disp.eq(self.tx_fifos.disp_out[self.tx_fifos.pe.o]), disp.eq(self.tx_fifos.disp_out[self.tx_fifos.pe.o]),
).Else( ).Else(
idling.eq(1), idling.eq(1),
idle_ack.eq(1),
tx_reg.eq(self.encoder.output), tx_reg.eq(self.encoder.output),
disp.eq(self.encoder.disp_out), disp.eq(self.encoder.disp_out),
) )
@ -148,6 +164,7 @@ class CXP_UpConn(Module, AutoCSR):
tx_reg.eq(self.tx_fifos.source_data[priority]), tx_reg.eq(self.tx_fifos.source_data[priority]),
disp.eq(self.tx_fifos.disp_out[priority]), disp.eq(self.tx_fifos.disp_out[priority]),
).Else( ).Else(
idle_ack.eq(1),
tx_reg.eq(self.encoder.output), tx_reg.eq(self.encoder.output),
disp.eq(self.encoder.disp_out), disp.eq(self.encoder.disp_out),
) )
@ -174,7 +191,7 @@ class CXP_UpConn(Module, AutoCSR):
p2 = Signal() p2 = Signal()
self.comb += [ self.comb += [
ninth_bit.eq(tx_bitcount == 9), ninth_bit.eq(tx_bitcount == 9),
word_bound.eq(tx_wordcount == 0), word_bound.eq(tx_wordcount == 3),
p1.eq(priority == 1), p1.eq(priority == 1),
p2.eq(priority == 2), p2.eq(priority == 2),
] ]